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RISCV64Assembler.h
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2535 lines (2077 loc) · 94.2 KB
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/*
* Copyright (C) 2021 Igalia S.L.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#pragma once
#if ENABLE(ASSEMBLER) && CPU(RISCV64)
#include "AssemblerBuffer.h"
#include "RISCV64Registers.h"
#include <tuple>
namespace JSC {
namespace RISCV64Registers {
typedef enum : int8_t {
#define REGISTER_ID(id, name, r, cs) id,
FOR_EACH_GP_REGISTER(REGISTER_ID)
#undef REGISTER_ID
#define REGISTER_ALIAS(id, name, alias) id = alias,
FOR_EACH_REGISTER_ALIAS(REGISTER_ALIAS)
#undef REGISTER_ALIAS
InvalidGPRReg = -1,
} RegisterID;
typedef enum : int8_t {
#define REGISTER_ID(id, name) id,
FOR_EACH_SP_REGISTER(REGISTER_ID)
#undef REGISTER_ID
InvalidSPReg = -1,
} SPRegisterID;
typedef enum : int8_t {
#define REGISTER_ID(id, name, r, cs) id,
FOR_EACH_FP_REGISTER(REGISTER_ID)
#undef REGISTER_ID
InvalidFPRReg = -1,
} FPRegisterID;
} // namespace RISCV64Registers
namespace RISCV64Instructions {
enum class Opcode : unsigned {
LOAD = 0b0000011,
LOAD_FP = 0b0000111,
MISC_MEM = 0b0001111,
OP_IMM = 0b0010011,
AUIPC = 0b0010111,
OP_IMM_32 = 0b0011011,
STORE = 0b0100011,
STORE_FP = 0b0100111,
AMO = 0b0101111,
OP = 0b0110011,
LUI = 0b0110111,
OP_32 = 0b0111011,
MADD = 0b1000011,
MSUB = 0b1000111,
NMSUB = 0b1001011,
NMADD = 0b1001111,
OP_FP = 0b1010011,
BRANCH = 0b1100011,
JALR = 0b1100111,
JAL = 0b1101111,
SYSTEM = 0b1110011,
};
enum class FCVTType {
W, WU,
L, LU,
S, D,
};
enum class FMVType {
X, W, D,
};
enum class FPRoundingMode : unsigned {
RNE = 0b000,
RTZ = 0b001,
RDN = 0b010,
RUP = 0b011,
RMM = 0b100,
DYN = 0b111,
};
enum class MemoryOperation : uint8_t {
I = 1 << 3,
O = 1 << 2,
R = 1 << 1,
W = 1 << 0,
RW = R | W,
IORW = I | O | R | W,
};
enum class MemoryAccess : uint8_t {
Acquire = 1 << 1,
Release = 1 << 0,
AcquireRelease = Acquire | Release,
};
// Register helpers
using RegisterID = RISCV64Registers::RegisterID;
using FPRegisterID = RISCV64Registers::FPRegisterID;
template<typename T>
auto registerValue(T registerID)
-> std::enable_if_t<(std::is_same_v<T, RegisterID> || std::is_same_v<T, FPRegisterID>), unsigned>
{
return unsigned(registerID) & ((1 << 5) - 1);
}
// InstructionValue contains the 32-bit instruction value and also provides access into the desired field.
struct InstructionValue {
explicit InstructionValue(uint32_t value)
: value(value)
{ }
template<unsigned fieldStart, unsigned fieldSize>
uint32_t field()
{
static_assert(fieldStart + fieldSize <= (sizeof(uint32_t) * 8));
return (value >> fieldStart) & ((1 << fieldSize) - 1);
}
uint32_t opcode() { return field<0, 7>(); }
uint32_t value;
};
// Immediate types
// ImmediateBase acts as the base struct for the different types. The bit-size of the immediate is determined as the
// template parameter on the ImmediateBase struct. Internally, every immediate value is represented through a uint32_t
// from which the appropriate bit-sets are then copied into the target instruction.
// ImmediateBase provides three ways to construct the target immediate (the type of which is specified as a template
// parameter to these construction methods):
// ImmediateBase<N>::v<ImmediateType, int32_t>() -- for constant immediates
// ImmediateBase<N>::v<ImmediateType>(int32_t/int64_t) -- for variable immediates whose values were validated beforehand
// ImmediateBase<N>::ImmediateBase(uint32_t) -- for immediate values already packed in the uint32_t format
// There's also ImmediateType::value(InstructionValue) helpers that for a given instruction value retrieve the
// appropriate signed immediate value that was encoded in that instruction (except for the U-type immediate which is
// a 32-bit unsigned value).
template<unsigned immediateSize>
struct ImmediateBase {
static_assert(immediateSize <= sizeof(uint32_t) * 8);
template<typename T>
static constexpr T immediateMask()
{
if constexpr(immediateSize < sizeof(uint32_t) * 8)
return ((T(1) << immediateSize) - 1);
return T(~0);
}
template<typename T>
static auto isValid(T immValue)
-> std::enable_if_t<(std::is_same_v<T, int32_t> || std::is_same_v<T, int64_t>), bool>
{
constexpr unsigned shift = sizeof(T) * 8 - immediateSize;
return immValue == ((immValue << shift) >> shift);
}
template<typename ImmediateType, int32_t immValue>
static ImmediateType v()
{
static_assert((-(1 << (immediateSize - 1)) <= immValue) && (immValue <= ((1 << (immediateSize - 1)) - 1)));
int32_t value = immValue;
return ImmediateType((*reinterpret_cast<uint32_t*>(&value)) & immediateMask<uint32_t>());
}
template<typename ImmediateType>
static ImmediateType v(int32_t immValue)
{
ASSERT(isValid(immValue));
uint32_t value = *reinterpret_cast<uint32_t*>(&immValue);
return ImmediateType(value & immediateMask<uint32_t>());
}
template<typename ImmediateType>
static ImmediateType v(int64_t immValue)
{
ASSERT(isValid(immValue));
uint64_t value = *reinterpret_cast<uint64_t*>(&immValue);
return ImmediateType(uint32_t(value & immediateMask<uint64_t>()));
}
explicit ImmediateBase(uint32_t immValue)
: imm(immValue)
{
if constexpr (immediateSize < sizeof(uint32_t) * 8)
ASSERT(imm < (1 << immediateSize));
}
template<unsigned fieldStart, unsigned fieldSize>
uint32_t field()
{
static_assert(fieldStart + fieldSize <= immediateSize);
return (imm >> fieldStart) & ((1 << fieldSize) - 1);
}
uint32_t imm;
};
struct IImmediate : ImmediateBase<12> {
explicit IImmediate(uint32_t immValue)
: ImmediateBase<12>(immValue)
{ }
static int32_t value(InstructionValue insn)
{
uint32_t base = insn.field<20, 12>();
int32_t imm = *reinterpret_cast<int32_t*>(&base);
return ((imm << 20) >> 20);
}
};
struct SImmediate : ImmediateBase<12> {
explicit SImmediate(uint32_t immValue)
: ImmediateBase<12>(immValue)
{ }
static int32_t value(InstructionValue insn)
{
uint32_t base = 0
| (insn.field<31, 1>() << 11)
| (insn.field<25, 6>() << 5)
| (insn.field< 8, 4>() << 1)
| (insn.field< 7, 1>() << 0);
int32_t imm = *reinterpret_cast<int32_t*>(&base);
return ((imm << 20) >> 20);
}
};
struct BImmediate : ImmediateBase<13> {
explicit BImmediate(uint32_t immValue)
: ImmediateBase<13>(immValue)
{ }
static int32_t value(InstructionValue insn)
{
uint32_t base = 0
| (insn.field<31, 1>() << 12)
| (insn.field< 7, 1>() << 11)
| (insn.field<25, 6>() << 5)
| (insn.field< 8, 4>() << 1);
int32_t imm = *reinterpret_cast<int32_t*>(&base);
return ((imm << 19) >> 19);
}
};
struct UImmediate : ImmediateBase<32> {
explicit UImmediate(uint32_t immValue)
: ImmediateBase((immValue >> 12) << 12)
{ }
static uint32_t value(InstructionValue insn)
{
return insn.field<12, 20>() << 12;
}
};
struct JImmediate : ImmediateBase<21> {
explicit JImmediate(uint32_t immValue)
: ImmediateBase<21>(immValue)
{ }
static int32_t value(InstructionValue insn)
{
uint32_t base = 0
| (insn.field<31, 1>() << 20)
| (insn.field<12, 8>() << 12)
| (insn.field<20, 1>() << 11)
| (insn.field<25, 6>() << 5)
| (insn.field<21, 4>() << 1);
int32_t imm = *reinterpret_cast<int32_t*>(&base);
return ((imm << 11) >> 11);
}
};
struct ImmediateDecomposition {
template<typename T, typename = std::enable_if_t<(std::is_same_v<T, int32_t> || std::is_same_v<T, int64_t>)>>
explicit ImmediateDecomposition(T immediate)
: upper(UImmediate(0))
, lower(IImmediate(0))
{
ASSERT(ImmediateBase<32>::isValid(immediate));
int32_t value = int32_t(immediate);
if (value & (1 << 11))
value += (1 << 12);
upper = UImmediate::v<UImmediate>(value);
lower = IImmediate::v<IImmediate>((value << 20) >> 20);
}
UImmediate upper;
IImmediate lower;
};
// Instruction types
// Helper struct that provides different groupings of register types as required for different instructions.
// The tuple size and contained types are used for compile-time checks of matching register types being passed
// to those instructions.
struct RegistersBase {
struct GType { }; // General-purpose register
struct FType { }; // Floating-point register
struct ZType { }; // Zero-value unused register
template<typename... RTypes>
using Tuple = std::tuple<RTypes...>;
template<size_t I, typename TupleType>
using Type = std::tuple_element_t<I, TupleType>;
template<typename TupleType>
static constexpr size_t Size()
{
return std::tuple_size_v<TupleType>;
}
using G = Tuple<GType>;
using GG = Tuple<GType, GType>;
using GF = Tuple<GType, FType>;
using GGG = Tuple<GType, GType, GType>;
using GGZ = Tuple<GType, GType, ZType>;
using GFF = Tuple<GType, FType, FType>;
using GFZ = Tuple<GType, FType, ZType>;
using FG = Tuple<FType, GType>;
using FF = Tuple<FType, FType>;
using FGZ = Tuple<FType, GType, ZType>;
using FFF = Tuple<FType, FType, FType>;
using FFZ = Tuple<FType, FType, ZType>;
using FFFF = Tuple<FType, FType, FType, FType>;
using ZZ = Tuple<ZType, ZType>;
};
// These are the base instruction structs. For R-type instructions, additional variations are provided.
// Opcode, different spec-defined constant instruction fields and the required register types are specified through the
// template parameters. The construct() static methods compose and return the instruction value in the 32-bit unsigned
// format.
// The matches() methods are usable to match a given InstructionValue against the target instruction type. Baseline
// implementations test the opcode and constant fields, but different instruction specializations can provide a better
// matching technique if necessary.
// For each base instruction type there's also static getters for dynamic bit-fields like register values, rounding mode
// or different flag types. These should be used on an InstructionValue after a matching instruction type was already
// confirmed. These are mostly used for disassembly, leaving it to that implementation to handle the returned raw
// bit-field values.
template<typename RegisterTypes>
struct RTypeRegisters {
static_assert(RegistersBase::Size<RegisterTypes>() == 3);
using RD = RegistersBase::Type<0, RegisterTypes>;
using RS1 = RegistersBase::Type<1, RegisterTypes>;
using RS2 = RegistersBase::Type<2, RegisterTypes>;
};
template<Opcode opcode, unsigned funct3, unsigned funct7, typename RegisterTypes>
struct RTypeBase {
static_assert(unsigned(opcode) < (1 << 7));
static_assert(funct3 < (1 << 3));
static_assert(funct7 < (1 << 7));
using Base = RTypeBase<opcode, funct3, funct7, RegisterTypes>;
using Registers = RTypeRegisters<RegisterTypes>;
template<typename RDType, typename RS1Type, typename RS2Type>
static uint32_t construct(RDType rd, RS1Type rs1, RS2Type rs2)
{
uint32_t instruction = 0
| (funct7 << 25)
| (registerValue(rs2) << 20)
| (registerValue(rs1) << 15)
| (funct3 << 12)
| (registerValue(rd) << 7)
| unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode() && funct3 == insn.field<12, 3>() && funct7 == insn.field<25, 7>();
}
static uint8_t rd(InstructionValue insn) { return insn.field<7, 5>(); }
static uint8_t rs1(InstructionValue insn) { return insn.field<15, 5>(); }
static uint8_t rs2(InstructionValue insn) { return insn.field<20, 5>(); }
};
template<Opcode opcode, unsigned funct7, typename RegisterTypes>
struct RTypeBaseWithRoundingMode {
static_assert(unsigned(opcode) < (1 << 7));
static_assert(funct7 < (1 << 7));
using Base = RTypeBaseWithRoundingMode<opcode, funct7, RegisterTypes>;
using Registers = RTypeRegisters<RegisterTypes>;
template<typename RDType, typename RS1Type, typename RS2Type>
static uint32_t construct(RDType rd, RS1Type rs1, RS2Type rs2, FPRoundingMode rm)
{
ASSERT(unsigned(rm) < (1 << 3));
uint32_t instruction = 0
| (funct7 << 25)
| (registerValue(rs2) << 20)
| (registerValue(rs1) << 15)
| (unsigned(rm) << 12)
| (registerValue(rd) << 7)
| unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode() && funct7 == insn.field<25, 7>();
}
static uint8_t rd(InstructionValue insn) { return insn.field<7, 5>(); }
static uint8_t rs1(InstructionValue insn) { return insn.field<15, 5>(); }
static uint8_t rs2(InstructionValue insn) { return insn.field<20, 5>(); }
static uint8_t rm(InstructionValue insn) { return insn.field<12, 3>(); }
};
template<Opcode opcode, unsigned funct3, unsigned funct7, typename RegisterTypes>
struct RTypeBaseWithAqRl {
static_assert(unsigned(opcode) < (1 << 7));
static_assert(funct3 < (1 << 3));
static_assert(funct7 < (1 << 7));
using Base = RTypeBaseWithAqRl<opcode, funct3, funct7, RegisterTypes>;
using Registers = RTypeRegisters<RegisterTypes>;
template<typename RDType, typename RS1Type, typename RS2Type>
static uint32_t construct(RDType rd, RS1Type rs1, RS2Type rs2, const std::initializer_list<MemoryAccess>& access)
{
unsigned aqrl = 0;
for (auto& value : access)
aqrl |= unsigned(value);
ASSERT(aqrl < (1 << 2));
uint32_t instruction = 0
| ((funct7 | aqrl) << 25)
| (registerValue(rs2) << 20)
| (registerValue(rs1) << 15)
| (funct3 << 12)
| (registerValue(rd) << 7)
| unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode() && funct3 == insn.field<12, 3>() && (funct7 >> 2) == insn.field<27, 5>();
}
static uint8_t rd(InstructionValue insn) { return insn.field<7, 5>(); }
static uint8_t rs1(InstructionValue insn) { return insn.field<15, 5>(); }
static uint8_t rs2(InstructionValue insn) { return insn.field<20, 5>(); }
static uint8_t aqrl(InstructionValue insn) { return insn.field<25, 2>(); }
};
template<typename RegisterTypes>
struct R4TypeRegisters {
static_assert(RegistersBase::Size<RegisterTypes>() == 4);
using RD = RegistersBase::Type<0, RegisterTypes>;
using RS1 = RegistersBase::Type<1, RegisterTypes>;
using RS2 = RegistersBase::Type<2, RegisterTypes>;
using RS3 = RegistersBase::Type<3, RegisterTypes>;
};
template<Opcode opcode, unsigned funct2, typename RegisterTypes>
struct R4TypeBaseWithRoundingMode {
static_assert(unsigned(opcode) < (1 << 7));
static_assert(funct2 < (1 << 2));
using Base = R4TypeBaseWithRoundingMode<opcode, funct2, RegisterTypes>;
using Registers = R4TypeRegisters<RegisterTypes>;
template<typename RDType, typename RS1Type, typename RS2Type, typename RS3Type>
static uint32_t construct(RDType rd, RS1Type rs1, RS2Type rs2, RS3Type rs3, FPRoundingMode rm)
{
ASSERT(unsigned(rm) < (1 << 3));
uint32_t instruction = 0
| (registerValue(rs3) << 27)
| (funct2 << 25)
| (registerValue(rs2) << 20)
| (registerValue(rs1) << 15)
| (unsigned(rm) << 12)
| (registerValue(rd) << 7)
| unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode() && funct2 == insn.field<25, 2>();
}
static uint8_t rd(InstructionValue insn) { return insn.field<7, 5>(); }
static uint8_t rs1(InstructionValue insn) { return insn.field<15, 5>(); }
static uint8_t rs2(InstructionValue insn) { return insn.field<20, 5>(); }
static uint8_t rs3(InstructionValue insn) { return insn.field<27, 5>(); }
static uint8_t rm(InstructionValue insn) { return insn.field<12, 3>(); }
};
template<typename RegisterTypes>
struct ITypeRegisters {
static_assert(RegistersBase::Size<RegisterTypes>() == 2);
using RD = RegistersBase::Type<0, RegisterTypes>;
using RS1 = RegistersBase::Type<1, RegisterTypes>;
};
template<Opcode opcode, unsigned funct3, typename RegisterTypes>
struct ITypeBase {
static_assert(unsigned(opcode) < (1 << 7));
static_assert(funct3 < (1 << 3));
using Base = ITypeBase<opcode, funct3, RegisterTypes>;
using Registers = ITypeRegisters<RegisterTypes>;
template<typename RDType, typename RS1Type>
static uint32_t construct(RDType rd, RS1Type rs1, IImmediate imm)
{
uint32_t instruction = 0
| (imm.field<0, 12>() << 20)
| (registerValue(rs1) << 15)
| (funct3 << 12)
| (registerValue(rd) << 7)
| unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode() && funct3 == insn.field<12, 3>();
}
static uint8_t rd(InstructionValue insn) { return insn.field<7, 5>(); }
static uint8_t rs1(InstructionValue insn) { return insn.field<15, 5>(); }
};
template<typename RegisterTypes>
struct STypeRegisters {
static_assert(RegistersBase::Size<RegisterTypes>() == 2);
using RS1 = RegistersBase::Type<0, RegisterTypes>;
using RS2 = RegistersBase::Type<1, RegisterTypes>;
};
template<Opcode opcode, unsigned funct3, typename RegisterTypes>
struct STypeBase {
static_assert(unsigned(opcode) < (1 << 7));
static_assert(funct3 < (1 << 3));
using Base = STypeBase<opcode, funct3, RegisterTypes>;
using Registers = STypeRegisters<RegisterTypes>;
template<typename RS1Type, typename RS2Type>
static uint32_t construct(RS1Type rs1, RS2Type rs2, SImmediate imm)
{
uint32_t instruction = 0
| (imm.field<5, 7>() << 25)
| (registerValue(rs2) << 20)
| (registerValue(rs1) << 15)
| (funct3 << 12)
| (imm.field<0, 5>() << 7)
| unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode() && funct3 == insn.field<12, 3>();
}
static uint8_t rs1(InstructionValue insn) { return insn.field<15, 5>(); }
static uint8_t rs2(InstructionValue insn) { return insn.field<20, 5>(); }
};
template<typename RegisterTypes>
struct BTypeRegisters {
static_assert(RegistersBase::Size<RegisterTypes>() == 2);
using RS1 = RegistersBase::Type<0, RegisterTypes>;
using RS2 = RegistersBase::Type<1, RegisterTypes>;
};
template<Opcode opcode, unsigned funct3, typename RegisterTypes>
struct BTypeBase {
static_assert(unsigned(opcode) < (1 << 7));
static_assert(funct3 < (1 << 3));
using Base = BTypeBase<opcode, funct3, RegisterTypes>;
using Registers = BTypeRegisters<RegisterTypes>;
static constexpr unsigned funct3Value = funct3;
template<typename RS1Type, typename RS2Type>
static uint32_t construct(RS1Type rs1, RS2Type rs2, BImmediate imm)
{
uint32_t instruction = 0
| (imm.field<12, 1>() << 31)
| (imm.field< 5, 6>() << 25)
| (registerValue(rs2) << 20)
| (registerValue(rs1) << 15)
| (funct3 << 12)
| (imm.field< 1, 4>() << 8)
| (imm.field<11, 1>() << 7)
| unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode() && funct3 == insn.field<12, 3>();
}
static uint8_t rs1(InstructionValue insn) { return insn.field<15, 5>(); }
static uint8_t rs2(InstructionValue insn) { return insn.field<20, 5>(); }
};
template<typename RegisterTypes>
struct UTypeRegisters {
static_assert(RegistersBase::Size<RegisterTypes>() == 1);
using RD = RegistersBase::Type<0, RegisterTypes>;
};
template<Opcode opcode, typename RegisterTypes>
struct UTypeBase {
static_assert(unsigned(opcode) < (1 << 7));
using Base = UTypeBase<opcode, RegisterTypes>;
using Registers = UTypeRegisters<RegisterTypes>;
template<typename RDType>
static uint32_t construct(RDType rd, UImmediate imm)
{
uint32_t instruction = imm.imm | (registerValue(rd) << 7) | unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode();
}
static uint8_t rd(InstructionValue insn) { return insn.field<7, 5>(); }
};
template<typename RegisterTypes>
struct JTypeRegisters {
static_assert(RegistersBase::Size<RegisterTypes>() == 1);
using RD = RegistersBase::Type<0, RegisterTypes>;
};
template<Opcode opcode, typename RegisterTypes>
struct JTypeBase {
static_assert(unsigned(opcode) < (1 << 7));
using Base = JTypeBase<opcode, RegisterTypes>;
using Registers = UTypeRegisters<RegisterTypes>;
template<typename RDType>
static uint32_t construct(RDType rd, JImmediate imm)
{
uint32_t instruction = 0
| (imm.field<20, 1>() << 31)
| (imm.field< 1, 10>() << 21)
| (imm.field<11, 1>() << 20)
| (imm.field<12, 8>() << 12)
| (registerValue(rd) << 7)
| unsigned(opcode);
return instruction;
}
static bool matches(InstructionValue insn)
{
return unsigned(opcode) == insn.opcode();
}
static uint8_t rd(InstructionValue insn) { return insn.field<7, 5>(); }
};
// The following instruction definitions utilize the base instruction structs, in most cases specifying everything
// necessary in the template parameters of the base instruction struct they are inheriting from. For each instruction
// there's also a pretty-print name constant included in the definition, for use by the disassembler.
// RV32I Base Instruction Set
struct LUI : UTypeBase<Opcode::LUI, RegistersBase::G> {
static constexpr const char* name = "lui";
};
struct AUIPC : UTypeBase<Opcode::AUIPC, RegistersBase::G> {
static constexpr const char* name = "auipc";
};
struct JAL : JTypeBase<Opcode::JAL, RegistersBase::G> {
static constexpr const char* name = "jal";
};
struct JALR : ITypeBase<Opcode::JALR, 0b000, RegistersBase::GG> {
static constexpr const char* name = "jalr";
};
struct BEQ : BTypeBase<Opcode::BRANCH, 0b000, RegistersBase::GG> {
static constexpr const char* name = "beq";
};
struct BNE : BTypeBase<Opcode::BRANCH, 0b001, RegistersBase::GG> {
static constexpr const char* name = "bne";
};
struct BLT : BTypeBase<Opcode::BRANCH, 0b100, RegistersBase::GG> {
static constexpr const char* name = "blt";
};
struct BGE : BTypeBase<Opcode::BRANCH, 0b101, RegistersBase::GG> {
static constexpr const char* name = "bge";
};
struct BLTU : BTypeBase<Opcode::BRANCH, 0b110, RegistersBase::GG> {
static constexpr const char* name = "bltu";
};
struct BGEU : BTypeBase<Opcode::BRANCH, 0b111, RegistersBase::GG> {
static constexpr const char* name = "bgeu";
};
struct LB : ITypeBase<Opcode::LOAD, 0b000, RegistersBase::GG> {
static constexpr const char* name = "lb";
};
struct LH : ITypeBase<Opcode::LOAD, 0b001, RegistersBase::GG> {
static constexpr const char* name = "lh";
};
struct LW : ITypeBase<Opcode::LOAD, 0b010, RegistersBase::GG> {
static constexpr const char* name = "lw";
};
struct LBU : ITypeBase<Opcode::LOAD, 0b100, RegistersBase::GG> {
static constexpr const char* name = "lbu";
};
struct LHU : ITypeBase<Opcode::LOAD, 0b101, RegistersBase::GG> {
static constexpr const char* name = "lhu";
};
struct SB : STypeBase<Opcode::STORE, 0b000, RegistersBase::GG> {
static constexpr const char* name = "sb";
};
struct SH : STypeBase<Opcode::STORE, 0b001, RegistersBase::GG> {
static constexpr const char* name = "sh";
};
struct SW : STypeBase<Opcode::STORE, 0b010, RegistersBase::GG> {
static constexpr const char* name = "sw";
};
struct ADDI : ITypeBase<Opcode::OP_IMM, 0b000, RegistersBase::GG> {
static constexpr const char* name = "addi";
};
struct SLTI : ITypeBase<Opcode::OP_IMM, 0b010, RegistersBase::GG> {
static constexpr const char* name = "slti";
};
struct SLTIU : ITypeBase<Opcode::OP_IMM, 0b011, RegistersBase::GG> {
static constexpr const char* name = "sltiu";
};
struct XORI : ITypeBase<Opcode::OP_IMM, 0b100, RegistersBase::GG> {
static constexpr const char* name = "xori";
};
struct ORI : ITypeBase<Opcode::OP_IMM, 0b110, RegistersBase::GG> {
static constexpr const char* name = "ori";
};
struct ANDI : ITypeBase<Opcode::OP_IMM, 0b111, RegistersBase::GG> {
static constexpr const char* name = "andi";
};
struct SLLI : ITypeBase<Opcode::OP_IMM, 0b001, RegistersBase::GG> {
static constexpr const char* name = "slli";
using Base::construct;
template<unsigned shiftAmount, typename RDType, typename RS1Type>
static uint32_t construct(RDType rd, RS1Type rs1)
{
static_assert(shiftAmount < (1 << 6));
return Base::construct(rd, rs1, IImmediate::v<IImmediate, (0b000000 << 6) | shiftAmount>());
}
};
struct SRLI : ITypeBase<Opcode::OP_IMM, 0b101, RegistersBase::GG> {
static constexpr const char* name = "srli";
using Base::construct;
template<unsigned shiftAmount, typename RDType, typename RS1Type>
static uint32_t construct(RDType rd, RS1Type rs1)
{
static_assert(shiftAmount < (1 << 6));
return Base::construct(rd, rs1, IImmediate::v<IImmediate, (0b000000 << 6) | shiftAmount>());
}
};
struct SRAI : ITypeBase<Opcode::OP_IMM, 0b101, RegistersBase::GG> {
static constexpr const char* name = "srai";
using Base::construct;
template<unsigned shiftAmount, typename RDType, typename RS1Type>
static uint32_t construct(RDType rd, RS1Type rs1)
{
static_assert(shiftAmount < (1 << 6));
return Base::construct(rd, rs1, IImmediate::v<IImmediate, (0b010000 << 6) | shiftAmount>());
}
};
struct ADD : RTypeBase<Opcode::OP, 0b000, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "add";
};
struct SUB : RTypeBase<Opcode::OP, 0b000, 0b0100000, RegistersBase::GGG> {
static constexpr const char* name = "sub";
};
struct SLL : RTypeBase<Opcode::OP, 0b001, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "sll";
};
struct SLT : RTypeBase<Opcode::OP, 0b010, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "slt";
};
struct SLTU : RTypeBase<Opcode::OP, 0b011, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "sltu";
};
struct XOR : RTypeBase<Opcode::OP, 0b100, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "xor";
};
struct SRL : RTypeBase<Opcode::OP, 0b101, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "srl";
};
struct SRA : RTypeBase<Opcode::OP, 0b101, 0b0100000, RegistersBase::GGG> {
static constexpr const char* name = "sra";
};
struct OR : RTypeBase<Opcode::OP, 0b110, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "or";
};
struct AND : RTypeBase<Opcode::OP, 0b111, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "and";
};
struct FENCE : ITypeBase<Opcode::MISC_MEM, 0b000, RegistersBase::ZZ> {
static constexpr const char* name = "fence";
};
struct ECALL : ITypeBase<Opcode::SYSTEM, 0b000, RegistersBase::ZZ> {
static constexpr const char* name = "ecall";
};
struct EBREAK : ITypeBase<Opcode::SYSTEM, 0b000, RegistersBase::ZZ> {
static constexpr const char* name = "ebreak";
};
// RV64I Base Instruction Set (in addition to RV32I)
struct LWU : ITypeBase<Opcode::LOAD, 0b110, RegistersBase::GG> {
static constexpr const char* name = "lwu";
};
struct LD : ITypeBase<Opcode::LOAD, 0b011, RegistersBase::GG> {
static constexpr const char* name = "ld";
};
struct SD : STypeBase<Opcode::STORE, 0b011, RegistersBase::GG> {
static constexpr const char* name = "sd";
};
struct ADDIW : ITypeBase<Opcode::OP_IMM_32, 0b000, RegistersBase::GG> {
static constexpr const char* name = "addiw";
};
struct SLLIW : ITypeBase<Opcode::OP_IMM_32, 0b001, RegistersBase::GG> {
static constexpr const char* name = "slliw";
using Base::construct;
template<unsigned shiftAmount, typename RDType, typename RS1Type>
static uint32_t construct(RDType rd, RS1Type rs1)
{
static_assert(shiftAmount < (1 << 5));
return Base::construct(rd, rs1, IImmediate::v<IImmediate, (0b0000000 << 5) | shiftAmount>());
}
};
struct SRLIW : ITypeBase<Opcode::OP_IMM_32, 0b101, RegistersBase::GG> {
static constexpr const char* name = "srliw";
using Base::construct;
template<unsigned shiftAmount, typename RDType, typename RS1Type>
static uint32_t construct(RDType rd, RS1Type rs1)
{
static_assert(shiftAmount < (1 << 5));
return Base::construct(rd, rs1, IImmediate::v<IImmediate, (0b0000000 << 5) | shiftAmount>());
}
};
struct SRAIW : ITypeBase<Opcode::OP_IMM_32, 0b101, RegistersBase::GG> {
static constexpr const char* name = "sraiw";
using Base::construct;
template<unsigned shiftAmount, typename RDType, typename RS1Type>
static uint32_t construct(RDType rd, RS1Type rs1)
{
static_assert(shiftAmount < (1 << 5));
return Base::construct(rd, rs1, IImmediate::v<IImmediate, (0b0100000 << 5) | shiftAmount>());
}
};
struct ADDW : RTypeBase<Opcode::OP_32, 0b000, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "addw";
};
struct SUBW : RTypeBase<Opcode::OP_32, 0b000, 0b0100000, RegistersBase::GGG> {
static constexpr const char* name = "subw";
};
struct SLLW : RTypeBase<Opcode::OP_32, 0b001, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "sllw";
};
struct SRLW : RTypeBase<Opcode::OP_32, 0b101, 0b0000000, RegistersBase::GGG> {
static constexpr const char* name = "srlw";
};
struct SRAW : RTypeBase<Opcode::OP_32, 0b101, 0b0100000, RegistersBase::GGG> {
static constexpr const char* name = "sraw";
};
// RV32/RV64 Zifencei Standard Extension
struct FENCE_I : ITypeBase<Opcode::MISC_MEM, 0b001, RegistersBase::ZZ> {
static constexpr const char* name = "fence.i";
};
// RV32M Standard Extension
struct MUL : RTypeBase<Opcode::OP, 0b000, 0b0000001, RegistersBase::GGG> {
static constexpr const char* name = "mul";
};
struct MULH : RTypeBase<Opcode::OP, 0b001, 0b0000001, RegistersBase::GGG> {
static constexpr const char* name = "mulh";
};
struct MULHSU : RTypeBase<Opcode::OP, 0b010, 0b0000001, RegistersBase::GGG> {
static constexpr const char* name = "mulhsu";
};