using Base = MacroAssemblerBase;

static constexpr RegisterID nextRegister(RegisterID reg)

{

return static_cast<RegisterID>(reg + 1);

}

static constexpr FPRegisterID nextFPRegister(FPRegisterID reg)

{

return static_cast<FPRegisterID>(reg + 1);

}

static constexpr unsigned registerIndex(RegisterID reg)

{

return reg - firstRegister();

}

static constexpr unsigned fpRegisterIndex(FPRegisterID reg)

{

return reg - firstFPRegister();

}

static constexpr unsigned registerIndex(FPRegisterID reg)

{

return fpRegisterIndex(reg) + numberOfRegisters();

}

static constexpr unsigned totalNumberOfRegisters()

{

return numberOfRegisters() + numberOfFPRegisters();

}

using MacroAssemblerBase::pop;

using MacroAssemblerBase::jump;

using MacroAssemblerBase::farJump;

using MacroAssemblerBase::branch32;

using MacroAssemblerBase::compare32;

using MacroAssemblerBase::move;

using MacroAssemblerBase::moveDouble;

using MacroAssemblerBase::add32;

using MacroAssemblerBase::mul32;

using MacroAssemblerBase::and32;

using MacroAssemblerBase::branchAdd32;

using MacroAssemblerBase::branchMul32;

#if CPU(ARM64) || CPU(ARM_THUMB2) || CPU(X86_64) || CPU(MIPS) || CPU(RISCV64)

using MacroAssemblerBase::branchPtr;

#endif

#if CPU(X86_64)

using MacroAssemblerBase::branch64;

#endif

using MacroAssemblerBase::branchSub32;

using MacroAssemblerBase::lshift32;

using MacroAssemblerBase::or32;

using MacroAssemblerBase::rshift32;

using MacroAssemblerBase::store32;

using MacroAssemblerBase::sub32;

using MacroAssemblerBase::urshift32;

using MacroAssemblerBase::xor32;

#if CPU(ARM64) || CPU(X86_64) || CPU(RISCV64)

using MacroAssemblerBase::and64;

using MacroAssemblerBase::convertInt32ToDouble;

using MacroAssemblerBase::store64;

#endif

static bool isPtrAlignedAddressOffset(ptrdiff_t value)

{

return value == static_cast<int32_t>(value);

}

static const double twoToThe32; // This is super useful for some double code.

// Utilities used by the DFG JIT.

using AbstractMacroAssemblerBase::invert;

using MacroAssemblerBase::invert;

static DoubleCondition invert(DoubleCondition cond)

{

switch (cond) {

case DoubleEqualAndOrdered:

return DoubleNotEqualOrUnordered;

case DoubleNotEqualAndOrdered:

return DoubleEqualOrUnordered;

case DoubleGreaterThanAndOrdered:

return DoubleLessThanOrEqualOrUnordered;

case DoubleGreaterThanOrEqualAndOrdered:

return DoubleLessThanOrUnordered;

case DoubleLessThanAndOrdered:

return DoubleGreaterThanOrEqualOrUnordered;

case DoubleLessThanOrEqualAndOrdered:

return DoubleGreaterThanOrUnordered;

case DoubleEqualOrUnordered:

return DoubleNotEqualAndOrdered;

case DoubleNotEqualOrUnordered:

return DoubleEqualAndOrdered;

case DoubleGreaterThanOrUnordered:

return DoubleLessThanOrEqualAndOrdered;

case DoubleGreaterThanOrEqualOrUnordered:

return DoubleLessThanAndOrdered;

case DoubleLessThanOrUnordered:

return DoubleGreaterThanOrEqualAndOrdered;

case DoubleLessThanOrEqualOrUnordered:

return DoubleGreaterThanAndOrdered;

}

RELEASE_ASSERT_NOT_REACHED();

return DoubleEqualAndOrdered; // make compiler happy

}

static bool isInvertible(ResultCondition cond)

{

switch (cond) {

case Zero:

case NonZero:

case Signed:

case PositiveOrZero:

return true;

default:

return false;

}

}

static ResultCondition invert(ResultCondition cond)

{

switch (cond) {

case Zero:

return NonZero;

case NonZero:

return Zero;

case Signed:

return PositiveOrZero;

case PositiveOrZero:

return Signed;

default:

RELEASE_ASSERT_NOT_REACHED();

return Zero; // Make compiler happy for release builds.

}

}

static RelationalCondition flip(RelationalCondition cond)

{

switch (cond) {

case Equal:

case NotEqual:

return cond;

case Above:

return Below;

case AboveOrEqual:

return BelowOrEqual;

case Below:

return Above;

case BelowOrEqual:

return AboveOrEqual;

case GreaterThan:

return LessThan;

case GreaterThanOrEqual:

return LessThanOrEqual;

case LessThan:

return GreaterThan;

case LessThanOrEqual:

return GreaterThanOrEqual;

}

RELEASE_ASSERT_NOT_REACHED();

return Equal;

}

static bool isSigned(RelationalCondition cond)

{

return MacroAssemblerHelpers::isSigned<MacroAssembler>(cond);

}

static bool isUnsigned(RelationalCondition cond)

{

return MacroAssemblerHelpers::isUnsigned<MacroAssembler>(cond);

}

static bool isSigned(ResultCondition cond)

{

return MacroAssemblerHelpers::isSigned<MacroAssembler>(cond);

}

static bool isUnsigned(ResultCondition cond)

{

return MacroAssemblerHelpers::isUnsigned<MacroAssembler>(cond);

}

// Platform agnostic convenience functions,

// described in terms of other macro assembly methods.

void pop()

{

addPtr(TrustedImm32(sizeof(void*)), stackPointerRegister);

}

void peek(RegisterID dest, int index = 0)

{

loadPtr(Address(stackPointerRegister, (index * sizeof(void*))), dest);

}

Address addressForPoke(int index)

{

return Address(stackPointerRegister, (index * sizeof(void*)));

}

void poke(RegisterID src, int index = 0)

{

storePtr(src, addressForPoke(index));

}

void poke(TrustedImm32 value, int index = 0)

{

store32(value, addressForPoke(index));

}

void poke(TrustedImmPtr imm, int index = 0)

{

storePtr(imm, addressForPoke(index));

}

void poke(FPRegisterID src, int index = 0)

{

storeDouble(src, addressForPoke(index));

}

#if !CPU(ARM64)

void pushToSave(RegisterID src)

{

push(src);

}

void pushToSaveImmediateWithoutTouchingRegisters(TrustedImm32 imm)

{

push(imm);

}

void popToRestore(RegisterID dest)

{

pop(dest);

}

void pushToSave(FPRegisterID src)

{

subPtr(TrustedImm32(sizeof(double)), stackPointerRegister);

storeDouble(src, Address(stackPointerRegister));

}

void popToRestore(FPRegisterID dest)

{

loadDouble(Address(stackPointerRegister), dest);

addPtr(TrustedImm32(sizeof(double)), stackPointerRegister);

}

static constexpr ptrdiff_t pushToSaveByteOffset() { return sizeof(void*); }

#endif // !CPU(ARM64)

#if CPU(X86_64) || CPU(ARM64) || CPU(RISCV64)

void peek64(RegisterID dest, int index = 0)

{

load64(Address(stackPointerRegister, (index * sizeof(void*))), dest);

}

void poke(TrustedImm64 value, int index = 0)

{

store64(value, addressForPoke(index));

}

void poke64(RegisterID src, int index = 0)

{

store64(src, addressForPoke(index));

}

#endif

// Immediate shifts only have 5 controllable bits

// so we'll consider them safe for now.

TrustedImm32 trustedImm32ForShift(Imm32 imm)

{

return TrustedImm32(imm.asTrustedImm32().m_value & 31);

}

// Backwards banches, these are currently all implemented using existing forwards branch mechanisms.

void branchPtr(RelationalCondition cond, RegisterID op1, TrustedImmPtr imm, Label target)

{

branchPtr(cond, op1, imm).linkTo(target, this);

}

void branchPtr(RelationalCondition cond, RegisterID op1, ImmPtr imm, Label target)

{

branchPtr(cond, op1, imm).linkTo(target, this);

}

Jump branch32(RelationalCondition cond, RegisterID left, AbsoluteAddress right)

{

return branch32(flip(cond), right, left);

}

void branch32(RelationalCondition cond, RegisterID op1, RegisterID op2, Label target)

{

branch32(cond, op1, op2).linkTo(target, this);

}

void branch32(RelationalCondition cond, RegisterID op1, TrustedImm32 imm, Label target)

{

branch32(cond, op1, imm).linkTo(target, this);

}

void branch32(RelationalCondition cond, RegisterID op1, Imm32 imm, Label target)

{

branch32(cond, op1, imm).linkTo(target, this);

}

void branch32(RelationalCondition cond, RegisterID left, Address right, Label target)

{

branch32(cond, left, right).linkTo(target, this);

}

Jump branch32(RelationalCondition cond, TrustedImm32 left, RegisterID right)

{

return branch32(commute(cond), right, left);

}

Jump branch32(RelationalCondition cond, Imm32 left, RegisterID right)

{

return branch32(commute(cond), right, left);

}

void compare32(RelationalCondition cond, Imm32 left, RegisterID right, RegisterID dest)

{

compare32(commute(cond), right, left, dest);

}

void branchTestPtr(ResultCondition cond, RegisterID reg, Label target)

{

branchTestPtr(cond, reg).linkTo(target, this);

}

#if !CPU(ARM_THUMB2) && !CPU(ARM64)

PatchableJump patchableBranchPtr(RelationalCondition cond, Address left, TrustedImmPtr right = TrustedImmPtr(nullptr))

{

padBeforePatch();

return PatchableJump(branchPtr(cond, left, right));

}

PatchableJump patchableBranchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(nullptr))

{

padBeforePatch();

return PatchableJump(branchPtrWithPatch(cond, left, dataLabel, initialRightValue));

}

PatchableJump patchableBranch32WithPatch(RelationalCondition cond, Address left, DataLabel32& dataLabel, TrustedImm32 initialRightValue = TrustedImm32(0))

{

padBeforePatch();

return PatchableJump(branch32WithPatch(cond, left, dataLabel, initialRightValue));

}

PatchableJump patchableJump()

{

padBeforePatch();

return PatchableJump(jump());

}

PatchableJump patchableBranchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))

{

padBeforePatch();

return PatchableJump(branchTest32(cond, reg, mask));

}

PatchableJump patchableBranch32(RelationalCondition cond, RegisterID reg, TrustedImm32 imm)

{

padBeforePatch();

return PatchableJump(branch32(cond, reg, imm));

}

PatchableJump patchableBranch8(RelationalCondition cond, Address address, TrustedImm32 imm)

{

padBeforePatch();

return PatchableJump(branch8(cond, address, imm));

}

PatchableJump patchableBranch32(RelationalCondition cond, Address address, TrustedImm32 imm)

{

padBeforePatch();

return PatchableJump(branch32(cond, address, imm));

}

#endif

void jump(Label target)

{

jump().linkTo(target, this);

}

// Commute a relational condition, returns a new condition that will produce

// the same results given the same inputs but with their positions exchanged.

static RelationalCondition commute(RelationalCondition condition)

{

switch (condition) {

case Above:

return Below;

case AboveOrEqual:

return BelowOrEqual;

case Below:

return Above;

case BelowOrEqual:

return AboveOrEqual;

case GreaterThan:

return LessThan;

case GreaterThanOrEqual:

return LessThanOrEqual;

case LessThan:

return GreaterThan;

case LessThanOrEqual:

return GreaterThanOrEqual;

default:

break;

}

ASSERT(condition == Equal || condition == NotEqual);

return condition;

}

void oops()

{

abortWithReason(B3Oops);

}

// B3 has additional pseudo-opcodes for returning, when it wants to signal that the return

// consumes some register in some way.

void retVoid() { ret(); }

void ret32(RegisterID) { ret(); }

void ret64(RegisterID) { ret(); }

void retFloat(FPRegisterID) { ret(); }

void retDouble(FPRegisterID) { ret(); }

static constexpr unsigned BlindingModulus = 64;

bool shouldConsiderBlinding()

{

return !(random() & (BlindingModulus - 1));

}

void move(Address src, Address dest, RegisterID scratch)

{

loadPtr(src, scratch);

storePtr(scratch, dest);

}

void move32(Address src, Address dest, RegisterID scratch)

{

load32(src, scratch);

store32(scratch, dest);

}

void moveFloat(Address src, Address dest, FPRegisterID scratch)

{

loadFloat(src, scratch);

storeFloat(scratch, dest);

}

// Overload mostly for use in templates.

void move(FPRegisterID src, FPRegisterID dest)

{

moveDouble(src, dest);

}

void moveDouble(Address src, Address dest, FPRegisterID scratch)

{

loadDouble(src, scratch);

storeDouble(scratch, dest);

}

// Ptr methods

// On 32-bit platforms (i.e. x86), these methods directly map onto their 32-bit equivalents.

#if !CPU(ADDRESS64)

void addPtr(Address src, RegisterID dest)

{

add32(src, dest);

}

void addPtr(AbsoluteAddress src, RegisterID dest)

{

add32(src, dest);

}

void addPtr(RegisterID src, RegisterID dest)

{

add32(src, dest);

}

void addPtr(RegisterID left, RegisterID right, RegisterID dest)

{

add32(left, right, dest);

}

void addPtr(TrustedImm32 imm, RegisterID srcDest)

{

add32(imm, srcDest);

}

void addPtr(TrustedImmPtr imm, RegisterID dest)

{

add32(TrustedImm32(imm), dest);

}

void addPtr(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

add32(imm, src, dest);

}

void addPtr(TrustedImm32 imm, AbsoluteAddress address)

{

add32(imm, address);

}

void andPtr(RegisterID src, RegisterID dest)

{

and32(src, dest);

}

void andPtr(TrustedImm32 imm, RegisterID srcDest)

{

and32(imm, srcDest);

}

void andPtr(TrustedImmPtr imm, RegisterID srcDest)

{

and32(TrustedImm32(imm), srcDest);

}

void lshiftPtr(Imm32 imm, RegisterID srcDest)

{

lshift32(trustedImm32ForShift(imm), srcDest);

}

void lshiftPtr(TrustedImm32 imm, RegisterID srcDest)

{

lshift32(imm, srcDest);

}

void rshiftPtr(Imm32 imm, RegisterID srcDest)

{

rshift32(trustedImm32ForShift(imm), srcDest);

}

void rshiftPtr(TrustedImm32 imm, RegisterID srcDest)

{

rshift32(imm, srcDest);

}

void urshiftPtr(Imm32 imm, RegisterID srcDest)

{

urshift32(trustedImm32ForShift(imm), srcDest);

}

void urshiftPtr(RegisterID shiftAmmount, RegisterID srcDest)

{

urshift32(shiftAmmount, srcDest);

}

void negPtr(RegisterID dest)

{

neg32(dest);

}

void negPtr(RegisterID src, RegisterID dest)

{

neg32(src, dest);

}

void orPtr(RegisterID src, RegisterID dest)

{

or32(src, dest);

}

void orPtr(RegisterID op1, RegisterID op2, RegisterID dest)

{

or32(op1, op2, dest);

}

void orPtr(TrustedImmPtr imm, RegisterID dest)

{

or32(TrustedImm32(imm), dest);

}

void orPtr(TrustedImm32 imm, RegisterID dest)

{

or32(imm, dest);

}

void rotateRightPtr(TrustedImm32 imm, RegisterID srcDst)

{

rotateRight32(imm, srcDst);

}

void subPtr(RegisterID src, RegisterID dest)

{

sub32(src, dest);

}

void subPtr(RegisterID left, RegisterID right, RegisterID dest)

{

sub32(left, right, dest);

}

void subPtr(TrustedImm32 imm, RegisterID dest)

{

sub32(imm, dest);

}

void subPtr(RegisterID left, TrustedImm32 right, RegisterID dest)

{

sub32(left, right, dest);

}

void subPtr(TrustedImmPtr imm, RegisterID dest)

{

sub32(TrustedImm32(imm), dest);

}

void xorPtr(RegisterID src, RegisterID dest)

{

xor32(src, dest);

}

void xorPtr(TrustedImm32 imm, RegisterID srcDest)

{

xor32(imm, srcDest);

}

void xorPtr(TrustedImmPtr imm, RegisterID srcDest)

{

xor32(TrustedImm32(imm), srcDest);

}

void xorPtr(Address src, RegisterID dest)

{

xor32(src, dest);

}

void loadPtr(Address address, RegisterID dest)

{

load32(address, dest);

}

void loadPtr(BaseIndex address, RegisterID dest)

{

#if CPU(NEEDS_ALIGNED_ACCESS)

ASSERT(address.scale == ScalePtr || address.scale == TimesOne);

#endif

load32(address, dest);

}

void loadPtr(const void* address, RegisterID dest)

{

load32(address, dest);

}

#if ENABLE(FAST_TLS_JIT)

void loadFromTLSPtr(uint32_t offset, RegisterID dst)

{

loadFromTLS32(offset, dst);

}

void storeToTLSPtr(RegisterID src, uint32_t offset)

{

storeToTLS32(src, offset);

}

#endif

void comparePtr(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)

{

compare32(cond, left, right, dest);

}

void comparePtr(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)

{

compare32(cond, left, right, dest);

}

void storePtr(RegisterID src, Address address)

{

store32(src, address);

}

void storePtr(RegisterID src, BaseIndex address)

{

store32(src, address);

}

void storePtr(RegisterID src, void* address)

{

store32(src, address);

}

void storePtr(TrustedImmPtr imm, Address address)

{

store32(TrustedImm32(imm), address);

}

void storePtr(ImmPtr imm, Address address)

{

store32(Imm32(imm.asTrustedImmPtr()), address);

}

void storePtr(TrustedImmPtr imm, void* address)

{

store32(TrustedImm32(imm), address);

}

void storePtr(TrustedImm32 imm, Address address)

{

store32(imm, address);

}

void storePtr(TrustedImmPtr imm, BaseIndex address)

{

store32(TrustedImm32(imm), address);

}

Jump branchPtr(RelationalCondition cond, RegisterID left, RegisterID right)

{

return branch32(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, RegisterID left, TrustedImmPtr right)

{

return branch32(cond, left, TrustedImm32(right));

}

Jump branchPtr(RelationalCondition cond, RegisterID left, ImmPtr right)

{

return branch32(cond, left, Imm32(right.asTrustedImmPtr()));

}

Jump branchPtr(RelationalCondition cond, RegisterID left, Address right)

{

return branch32(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, Address left, RegisterID right)

{

return branch32(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, AbsoluteAddress left, RegisterID right)

{

return branch32(cond, left, right);

}

Jump branchPtr(RelationalCondition cond, Address left, TrustedImmPtr right)

{

return branch32(cond, left, TrustedImm32(right));

}

Jump branchPtr(RelationalCondition cond, AbsoluteAddress left, TrustedImmPtr right)

{

return branch32(cond, left, TrustedImm32(right));

}

Jump branchSubPtr(ResultCondition cond, RegisterID src, RegisterID dest)

{

return branchSub32(cond, src, dest);

}

Jump branchTestPtr(ResultCondition cond, RegisterID reg, RegisterID mask)

{

return branchTest32(cond, reg, mask);

}

Jump branchTestPtr(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest32(cond, reg, mask);

}

Jump branchTestPtr(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest32(cond, address, mask);

}

Jump branchTestPtr(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))

{

return branchTest32(cond, address, mask);

}

Jump branchAddPtr(ResultCondition cond, RegisterID src, RegisterID dest)

{

return branchAdd32(cond, src, dest);

}

Jump branchSubPtr(ResultCondition cond, TrustedImm32 imm, RegisterID dest)

{

return branchSub32(cond, imm, dest);

}

using MacroAssemblerBase::branchTest8;

Jump branchTest8(ResultCondition cond, ExtendedAddress address, TrustedImm32 mask = TrustedImm32(-1))

{

return MacroAssemblerBase::branchTest8(cond, Address(address.base, address.offset), mask);

}

using MacroAssemblerBase::branchTest16;

Jump branchTest16(ResultCondition cond, ExtendedAddress address, TrustedImm32 mask = TrustedImm32(-1))

{

return MacroAssemblerBase::branchTest16(cond, Address(address.base, address.offset), mask);

}

#else // !CPU(ADDRESS64)

void addPtr(RegisterID src, RegisterID dest)

{

add64(src, dest);

}

void addPtr(RegisterID left, RegisterID right, RegisterID dest)

{

add64(left, right, dest);

}

void addPtr(Address src, RegisterID dest)

{

add64(src, dest);

}

void addPtr(TrustedImm32 imm, RegisterID srcDest)

{

add64(imm, srcDest);

}

void addPtr(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

add64(imm, src, dest);

}

void addPtr(TrustedImm32 imm, Address address)

{

add64(imm, address);

}

void addPtr(AbsoluteAddress src, RegisterID dest)

{

add64(src, dest);

}

void addPtr(TrustedImmPtr imm, RegisterID dest)

{

add64(TrustedImm64(imm), dest);

}

void addPtr(TrustedImm32 imm, AbsoluteAddress address)

{

add64(imm, address);

}

void andPtr(RegisterID src, RegisterID dest)

{

and64(src, dest);

}

void andPtr(TrustedImm32 imm, RegisterID srcDest)

{

and64(imm, srcDest);

}

void andPtr(TrustedImmPtr imm, RegisterID srcDest)

{

and64(imm, srcDest);

}

void lshiftPtr(Imm32 imm, RegisterID srcDest)

{

lshift64(trustedImm32ForShift(imm), srcDest);

}

void lshiftPtr(TrustedImm32 imm, RegisterID srcDest)

{

lshift64(imm, srcDest);

}

void rshiftPtr(Imm32 imm, RegisterID srcDest)

{

rshift64(trustedImm32ForShift(imm), srcDest);

}

void rshiftPtr(TrustedImm32 imm, RegisterID srcDest)

{

rshift64(imm, srcDest);

}

void urshiftPtr(Imm32 imm, RegisterID srcDest)

{

urshift64(trustedImm32ForShift(imm), srcDest);

}

void urshiftPtr(RegisterID shiftAmmount, RegisterID srcDest)

{

urshift64(shiftAmmount, srcDest);

}

void negPtr(RegisterID dest)

{

neg64(dest);

}

void negPtr(RegisterID src, RegisterID dest)

{

neg64(src, dest);

}

void orPtr(RegisterID src, RegisterID dest)

{

or64(src, dest);

}

void orPtr(TrustedImm32 imm, RegisterID dest)

{