#define REGISTER_ID(id, name, r, cs) id,

FOR_EACH_GP_REGISTER(REGISTER_ID)

#undef REGISTER_ID

#define REGISTER_ALIAS(id, name, alias) id = alias,

#define REGISTER_ID(id, name) id,

FOR_EACH_SP_REGISTER(REGISTER_ID)

#undef REGISTER_ID

#define REGISTER_ID(id, name, r, cs) id,

FOR_EACH_FP_SINGLE_REGISTER(REGISTER_ID)

#undef REGISTER_ID

#define REGISTER_ID(id, name, r, cs) id,

FOR_EACH_FP_DOUBLE_REGISTER(REGISTER_ID)

#undef REGISTER_ID

InvalidFPRReg = -1,

#define REGISTER_ID(id, name, r, cs) id,

FOR_EACH_FP_QUAD_REGISTER(REGISTER_ID)

#undef REGISTER_ID

{

ASSERT(reg <= d15);

return (FPSingleRegisterID)(reg << 1);

{

ASSERT(reg <= d15);

return (FPSingleRegisterID)((reg << 1) + 1);

{

ASSERT(!(reg & 1));

return (FPDoubleRegisterID)(reg >> 1);

friend class ARMv7Assembler;

typedef uint8_t ThumbImmediateType;

static constexpr ThumbImmediateType TypeInvalid = 0;

static constexpr ThumbImmediateType TypeEncoded = 1;

static constexpr ThumbImmediateType TypeUInt16 = 2;

typedef union {

int16_t asInt;

struct {

unsigned imm8 : 8;

unsigned imm3 : 3;

unsigned i : 1;

unsigned imm4 : 4;

};

// If this is an encoded immediate, then it may describe a shift, or a pattern.

struct {

unsigned shiftValue7 : 7;

unsigned shiftAmount : 5;

};

struct {

unsigned immediate : 8;

unsigned pattern : 4;

};

} ThumbImmediateValue;

// byte0 contains least significant bit; not using an array to make client code endian agnostic.

typedef union {

int32_t asInt;

struct {

uint8_t byte0;

uint8_t byte1;

uint8_t byte2;

uint8_t byte3;

};

} PatternBytes;

ALWAYS_INLINE static void countLeadingZerosPartial(uint32_t& value, int32_t& zeros, const int N)

{

if (value & ~((1 << N) - 1)) /* check for any of the top N bits (of 2N bits) are set */

value >>= N; /* if any were set, lose the bottom N */

else /* if none of the top N bits are set, */

zeros += N; /* then we have identified N leading zeros */

}

static int32_t countLeadingZeros(uint32_t value)

{

if (!value)

return 32;

int32_t zeros = 0;

countLeadingZerosPartial(value, zeros, 16);

countLeadingZerosPartial(value, zeros, 8);

countLeadingZerosPartial(value, zeros, 4);

countLeadingZerosPartial(value, zeros, 2);

countLeadingZerosPartial(value, zeros, 1);

return zeros;

}

ARMThumbImmediate()

: m_type(TypeInvalid)

{

m_value.asInt = 0;

}

ARMThumbImmediate(ThumbImmediateType type, ThumbImmediateValue value)

: m_type(type)

, m_value(value)

{

}

ARMThumbImmediate(ThumbImmediateType type, uint16_t value)

: m_type(TypeUInt16)

{

// Make sure this constructor is only reached with type TypeUInt16;

// this extra parameter makes the code a little clearer by making it

// explicit at call sites which type is being constructed

ASSERT_UNUSED(type, type == TypeUInt16);

m_value.asInt = value;

}

static ARMThumbImmediate makeEncodedImm(uint32_t value)

{

ThumbImmediateValue encoding;

encoding.asInt = 0;

// okay, these are easy.

if (value < 256) {

encoding.immediate = value;

encoding.pattern = 0;

return ARMThumbImmediate(TypeEncoded, encoding);

}

int32_t leadingZeros = countLeadingZeros(value);

// if there were 24 or more leading zeros, then we'd have hit the (value < 256) case.

ASSERT(leadingZeros < 24);

// Given a number with bit fields Z:B:C, where count(Z)+count(B)+count(C) == 32,

// Z are the bits known zero, B is the 8-bit immediate, C are the bits to check for

// zero. count(B) == 8, so the count of bits to be checked is 24 - count(Z).

int32_t rightShiftAmount = 24 - leadingZeros;

if (value == ((value >> rightShiftAmount) << rightShiftAmount)) {

// Shift the value down to the low byte position. The assign to

// shiftValue7 drops the implicit top bit.

encoding.shiftValue7 = value >> rightShiftAmount;

// The endoded shift amount is the magnitude of a right rotate.

encoding.shiftAmount = 8 + leadingZeros;

return ARMThumbImmediate(TypeEncoded, encoding);

}

PatternBytes bytes;

bytes.asInt = value;

if ((bytes.byte0 == bytes.byte1) && (bytes.byte0 == bytes.byte2) && (bytes.byte0 == bytes.byte3)) {

encoding.immediate = bytes.byte0;

encoding.pattern = 3;

return ARMThumbImmediate(TypeEncoded, encoding);

}

if ((bytes.byte0 == bytes.byte2) && !(bytes.byte1 | bytes.byte3)) {

encoding.immediate = bytes.byte0;

encoding.pattern = 1;

return ARMThumbImmediate(TypeEncoded, encoding);

}

if ((bytes.byte1 == bytes.byte3) && !(bytes.byte0 | bytes.byte2)) {

encoding.immediate = bytes.byte1;

encoding.pattern = 2;

return ARMThumbImmediate(TypeEncoded, encoding);

}

return ARMThumbImmediate();

}

static ARMThumbImmediate makeUInt12(int32_t value)

{

return (!(value & 0xfffff000))

? ARMThumbImmediate(TypeUInt16, (uint16_t)value)

: ARMThumbImmediate();

}

static ARMThumbImmediate makeUInt12OrEncodedImm(int32_t value)

{

// If this is not a 12-bit unsigned it, try making an encoded immediate.

return (!(value & 0xfffff000))

? ARMThumbImmediate(TypeUInt16, (uint16_t)value)

: makeEncodedImm(value);

}

// The 'make' methods, above, return a !isValid() value if the argument

// cannot be represented as the requested type. This methods is called

// 'get' since the argument can always be represented.

static ARMThumbImmediate makeUInt16(uint16_t value)

{

return ARMThumbImmediate(TypeUInt16, value);

}

bool isValid()

{

return m_type != TypeInvalid;

}

uint16_t asUInt16() const { return m_value.asInt; }

// These methods rely on the format of encoded byte values.

bool isUInt3() { return !(m_value.asInt & 0xfff8); }

bool isUInt4() { return !(m_value.asInt & 0xfff0); }

bool isUInt5() { return !(m_value.asInt & 0xffe0); }

bool isUInt6() { return !(m_value.asInt & 0xffc0); }

bool isUInt7() { return !(m_value.asInt & 0xff80); }

bool isUInt8() { return !(m_value.asInt & 0xff00); }

bool isUInt9() { return (m_type == TypeUInt16) && !(m_value.asInt & 0xfe00); }

bool isUInt10() { return (m_type == TypeUInt16) && !(m_value.asInt & 0xfc00); }

bool isUInt12() { return (m_type == TypeUInt16) && !(m_value.asInt & 0xf000); }

bool isUInt16() { return m_type == TypeUInt16; }

uint8_t getUInt3() { ASSERT(isUInt3()); return m_value.asInt; }

uint8_t getUInt4() { ASSERT(isUInt4()); return m_value.asInt; }

uint8_t getUInt5() { ASSERT(isUInt5()); return m_value.asInt; }

uint8_t getUInt6() { ASSERT(isUInt6()); return m_value.asInt; }

uint8_t getUInt7() { ASSERT(isUInt7()); return m_value.asInt; }

uint8_t getUInt8() { ASSERT(isUInt8()); return m_value.asInt; }

uint16_t getUInt9() { ASSERT(isUInt9()); return m_value.asInt; }

uint16_t getUInt10() { ASSERT(isUInt10()); return m_value.asInt; }

uint16_t getUInt12() { ASSERT(isUInt12()); return m_value.asInt; }

uint16_t getUInt16() { ASSERT(isUInt16()); return m_value.asInt; }

bool isEncodedImm() { return m_type == TypeEncoded; }

ThumbImmediateType m_type;

ThumbImmediateValue m_value;

friend class ARMv7Assembler;

ShiftTypeAndAmount()

{

m_u.type = (ARMShiftType)0;

m_u.amount = 0;

}

ShiftTypeAndAmount(ARMShiftType type, unsigned amount)

{

m_u.type = type;

m_u.amount = amount & 31;

}

unsigned lo4() { return m_u.lo4; }

unsigned hi4() { return m_u.hi4; }

union {

struct {

unsigned lo4 : 4;

unsigned hi4 : 4;

};

struct {

unsigned type : 2;

unsigned amount : 6;

};

} m_u;

typedef ARMRegisters::RegisterID RegisterID;

typedef ARMRegisters::FPSingleRegisterID FPSingleRegisterID;

typedef ARMRegisters::FPDoubleRegisterID FPDoubleRegisterID;

#if CPU(ARM_NEON)

typedef ARMRegisters::FPQuadRegisterID FPQuadRegisterID;

#endif

typedef ARMRegisters::SPRegisterID SPRegisterID;

typedef FPDoubleRegisterID FPRegisterID;

static constexpr RegisterID firstRegister() { return ARMRegisters::r0; }

static constexpr RegisterID lastRegister() { return ARMRegisters::r15; }

static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; }

static constexpr SPRegisterID firstSPRegister() { return ARMRegisters::apsr; }

static constexpr SPRegisterID lastSPRegister() { return ARMRegisters::fpscr; }

static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; }

static constexpr FPRegisterID firstFPRegister() { return ARMRegisters::d0; }

#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)

static constexpr FPRegisterID lastFPRegister() { return ARMRegisters::d31; }

#else

static constexpr FPRegisterID lastFPRegister() { return ARMRegisters::d15; }

#endif

static constexpr unsigned numberOfFPRegisters() { return lastFPRegister() - firstFPRegister() + 1; }

static ASCIILiteral gprName(RegisterID id)

{

ASSERT(id >= firstRegister() && id <= lastRegister());

static constexpr ASCIILiteral nameForRegister[numberOfRegisters()] = {

#define REGISTER_NAME(id, name, r, cs) name,

FOR_EACH_GP_REGISTER(REGISTER_NAME)

#undef REGISTER_NAME

};

return nameForRegister[id];

}

static ASCIILiteral sprName(SPRegisterID id)

{

ASSERT(id >= firstSPRegister() && id <= lastSPRegister());

static constexpr ASCIILiteral nameForRegister[numberOfSPRegisters()] = {

#define REGISTER_NAME(id, name) name,

FOR_EACH_SP_REGISTER(REGISTER_NAME)

#undef REGISTER_NAME

};

return nameForRegister[id];

}

static ASCIILiteral fprName(FPRegisterID id)

{

ASSERT(id >= firstFPRegister() && id <= lastFPRegister());

static constexpr ASCIILiteral nameForRegister[numberOfFPRegisters()] = {

#define REGISTER_NAME(id, name, r, cs) name,

FOR_EACH_FP_DOUBLE_REGISTER(REGISTER_NAME)

#undef REGISTER_NAME

};

return nameForRegister[id];

}

// (HS, LO, HI, LS) -> (AE, B, A, BE)

// (VS, VC) -> (O, NO)

typedef enum {

ConditionEQ, // Zero / Equal.

ConditionNE, // Non-zero / Not equal.

ConditionHS, ConditionCS = ConditionHS, // Unsigned higher or same.

ConditionLO, ConditionCC = ConditionLO, // Unsigned lower.

ConditionMI, // Negative.

ConditionPL, // Positive or zero.

ConditionVS, // Overflowed.

ConditionVC, // Not overflowed.

ConditionHI, // Unsigned higher.

ConditionLS, // Unsigned lower or same.

ConditionGE, // Signed greater than or equal.

ConditionLT, // Signed less than.

ConditionGT, // Signed greater than.

ConditionLE, // Signed less than or equal.

ConditionAL, // Unconditional / Always execute.

ConditionInvalid

} Condition;

#define JUMP_ENUM_WITH_SIZE(index, value) (((value) << 3) | (index))

#define JUMP_ENUM_SIZE(jump) ((jump) >> 3)

enum JumpType { JumpFixed = JUMP_ENUM_WITH_SIZE(0, 0),

JumpNoCondition = JUMP_ENUM_WITH_SIZE(1, 5 * sizeof(uint16_t)),

JumpCondition = JUMP_ENUM_WITH_SIZE(2, 6 * sizeof(uint16_t)),

JumpNoConditionFixedSize = JUMP_ENUM_WITH_SIZE(3, 5 * sizeof(uint16_t)),

JumpConditionFixedSize = JUMP_ENUM_WITH_SIZE(4, 6 * sizeof(uint16_t))

};

enum JumpLinkType {

LinkInvalid = JUMP_ENUM_WITH_SIZE(0, 0),

LinkJumpT1 = JUMP_ENUM_WITH_SIZE(1, sizeof(uint16_t)),

LinkJumpT2 = JUMP_ENUM_WITH_SIZE(2, sizeof(uint16_t)),

LinkJumpT3 = JUMP_ENUM_WITH_SIZE(3, 2 * sizeof(uint16_t)),

LinkJumpT4 = JUMP_ENUM_WITH_SIZE(4, 2 * sizeof(uint16_t)),

LinkConditionalJumpT4 = JUMP_ENUM_WITH_SIZE(5, 3 * sizeof(uint16_t)),

LinkBX = JUMP_ENUM_WITH_SIZE(6, 5 * sizeof(uint16_t)),

LinkConditionalBX = JUMP_ENUM_WITH_SIZE(7, 6 * sizeof(uint16_t))

};

class LinkRecord {

public:

LinkRecord(intptr_t from, intptr_t to, JumpType type, Condition condition)

{

data.realTypes.m_from = from;

data.realTypes.m_to = to;

data.realTypes.m_type = type;

data.realTypes.m_linkType = LinkInvalid;

data.realTypes.m_condition = condition;

}

// We are defining a copy constructor and assignment operator

// because the ones provided by the compiler are not

// optimal. See https://bugs.webkit.org/show_bug.cgi?id=90930

LinkRecord(const LinkRecord& other)

{

data.copyTypes = other.data.copyTypes;

}

LinkRecord& operator=(const LinkRecord& other)

{

data.copyTypes = other.data.copyTypes;

return *this;

}

intptr_t from() const { return data.realTypes.m_from; }

void setFrom(const ARMv7Assembler*, intptr_t from) { data.realTypes.m_from = from; }

intptr_t to(const ARMv7Assembler*) const { return data.realTypes.m_to; }

JumpType type() const { return data.realTypes.m_type; }

JumpLinkType linkType() const { return data.realTypes.m_linkType; }

void setLinkType(JumpLinkType linkType) { ASSERT(data.realTypes.m_linkType == LinkInvalid); data.realTypes.m_linkType = linkType; }

Condition condition() const { return data.realTypes.m_condition; }

bool isThunk() const { return false; }

private:

union {

struct RealTypes {

intptr_t m_from : 31;

intptr_t m_to : 31;

JumpType m_type : 8;

JumpLinkType m_linkType : 8;

Condition m_condition : 16;

} realTypes;

struct CopyTypes {

uint32_t content[3];

} copyTypes;

static_assert(sizeof(RealTypes) == sizeof(CopyTypes), "LinkRecord's CopyStruct size equals to RealStruct");

} data;

};

ARMv7Assembler()

: m_indexOfLastWatchpoint(INT_MIN)

, m_indexOfTailOfLastWatchpoint(INT_MIN)

{

}

AssemblerBuffer& buffer() { return m_formatter.m_buffer; }

// In the ARMv7 ISA, the LSB of a code pointer indicates whether the target uses Thumb vs ARM

// encoding. These utility functions are there for when we need to deal with this.

static bool isEven(const void* ptr) { return !(reinterpret_cast<uintptr_t>(ptr) & 1); }

static bool isEven(AssemblerLabel &label) { return !(label.offset() & 1); }

static void* makeEven(const void* ptr)

{

ASSERT(!isEven(ptr));

return reinterpret_cast<void*>(reinterpret_cast<uintptr_t>(ptr) & ~1);

}

// ARMv7, Appx-A.6.3

static bool BadReg(RegisterID reg)

{

return (reg == ARMRegisters::sp) || (reg == ARMRegisters::pc);

}

uint32_t singleRegisterMask(FPSingleRegisterID rdNum, int highBitsShift, int lowBitShift)

{

uint32_t rdMask = (rdNum >> 1) << highBitsShift;

if (rdNum & 1)

rdMask |= 1 << lowBitShift;

return rdMask;

}

uint32_t doubleRegisterMask(FPDoubleRegisterID rdNum, int highBitShift, int lowBitsShift)

{

uint32_t rdMask = (rdNum & 0xf) << lowBitsShift;

if (rdNum & 16)

rdMask |= 1 << highBitShift;

return rdMask;

}

typedef enum {

OP_ADD_reg_T1 = 0x1800,

OP_SUB_reg_T1 = 0x1A00,

OP_ADD_imm_T1 = 0x1C00,

OP_SUB_imm_T1 = 0x1E00,

OP_MOV_imm_T1 = 0x2000,

OP_CMP_imm_T1 = 0x2800,

OP_ADD_imm_T2 = 0x3000,

OP_SUB_imm_T2 = 0x3800,

OP_AND_reg_T1 = 0x4000,

OP_EOR_reg_T1 = 0x4040,

OP_TST_reg_T1 = 0x4200,

OP_RSB_imm_T1 = 0x4240,

OP_CMP_reg_T1 = 0x4280,

OP_ORR_reg_T1 = 0x4300,

OP_MVN_reg_T1 = 0x43C0,

OP_ADD_reg_T2 = 0x4400,

OP_MOV_reg_T1 = 0x4600,

OP_BLX = 0x4700,

OP_BX = 0x4700,

OP_STR_reg_T1 = 0x5000,

OP_STRH_reg_T1 = 0x5200,

OP_STRB_reg_T1 = 0x5400,

OP_LDRSB_reg_T1 = 0x5600,

OP_LDR_reg_T1 = 0x5800,

OP_LDRH_reg_T1 = 0x5A00,

OP_LDRB_reg_T1 = 0x5C00,

OP_LDRSH_reg_T1 = 0x5E00,

OP_STR_imm_T1 = 0x6000,

OP_LDR_imm_T1 = 0x6800,

OP_STRB_imm_T1 = 0x7000,

OP_LDRB_imm_T1 = 0x7800,

OP_STRH_imm_T1 = 0x8000,

OP_LDRH_imm_T1 = 0x8800,

OP_STR_imm_T2 = 0x9000,

OP_LDR_imm_T2 = 0x9800,

OP_ADD_SP_imm_T1 = 0xA800,

OP_ADD_SP_imm_T2 = 0xB000,

OP_SUB_SP_imm_T1 = 0xB080,

OP_SXTH_T1 = 0xB200,

OP_SXTB_T1 = 0xB240,

OP_UXTH_T1 = 0xB280,

OP_UXTB_T1 = 0xB2C0,

OP_PUSH_T1 = 0xB400,

OP_POP_T1 = 0xBC00,

OP_BKPT = 0xBE00,

OP_IT = 0xBF00,

OP_NOP_T1 = 0xBF00,

OP_UDF = 0xDE00

} OpcodeID;

typedef enum {

OP_B_T1 = 0xD000,

OP_B_T2 = 0xE000,

OP_STRD_imm_T1 = 0xE840,

OP_STREX_T1 = 0xE840,

OP_LDRD_imm_T1 = 0xE850,

OP_LDREX_T1 = 0xE850,

OP_POP_T2 = 0xE8BD,

OP_STREXB_T1 = 0xE8C0,

OP_STREXD_T1 = 0xE8C0,

OP_STREXH_T1 = 0xE8C0,

OP_LDREXB_T1 = 0xE8D0,

OP_LDREXD_T1 = 0xE8D0,

OP_LDREXH_T1 = 0xE8D0,

OP_PUSH_T2 = 0xE92D,

OP_AND_reg_T2 = 0xEA00,

OP_TST_reg_T2 = 0xEA10,

OP_ORR_reg_T2 = 0xEA40,

OP_ORR_S_reg_T2 = 0xEA50,

OP_ASR_imm_T1 = 0xEA4F,

OP_LSL_imm_T1 = 0xEA4F,

OP_LSR_imm_T1 = 0xEA4F,

OP_ROR_imm_T1 = 0xEA4F,

OP_MVN_reg_T2 = 0xEA6F,

OP_EOR_reg_T2 = 0xEA80,

OP_ADD_reg_T3 = 0xEB00,

OP_ADD_S_reg_T3 = 0xEB10,

OP_ADC_reg_T2 = 0xEB40,

OP_SBC_reg_T2 = 0xEB60,

OP_SUB_reg_T2 = 0xEBA0,

OP_SUB_S_reg_T2 = 0xEBB0,

OP_CMP_reg_T2 = 0xEBB0,

OP_VMOV_CtoD = 0xEC00,

OP_VMOV_DtoC = 0xEC10,

OP_VSTMIA = 0xEC80,

OP_VLDMIA = 0xEC90,

OP_FSTS = 0xED00,

OP_VSTR = 0xED00,

OP_FLDS = 0xED10,

OP_VLDR = 0xED10,

OP_VMOV_CtoS = 0xEE00,

OP_VMOV_StoC = 0xEE10,

OP_VMUL_T2 = 0xEE20,

OP_VADD_T2 = 0xEE30,

OP_VSUB_T2 = 0xEE30,

OP_VDIV = 0xEE80,

OP_VABS_T2 = 0xEEB0,

OP_VCMP = 0xEEB0,

OP_VCVT_FPIVFP = 0xEEB0,

OP_VMOV_T2 = 0xEEB0,

OP_VMOV_IMM_T2 = 0xEEB0,

OP_VMRS = 0xEEB0,

OP_VNEG_T2 = 0xEEB0,

OP_VSQRT_T1 = 0xEEB0,

OP_VCVTSD_T1 = 0xEEB0,

OP_VCVTDS_T1 = 0xEEB0,

OP_VAND_T1 = 0xEF00,

OP_VORR_T1 = 0xEF20,

OP_B_T3a = 0xF000,

OP_B_T4a = 0xF000,

OP_BL_T4a = 0xF000,

OP_AND_imm_T1 = 0xF000,

OP_TST_imm = 0xF010,

OP_BIC_imm_T1 = 0xF020,

OP_ORR_imm_T1 = 0xF040,

OP_MOV_imm_T2 = 0xF040,

OP_MVN_imm = 0xF060,

OP_EOR_imm_T1 = 0xF080,

OP_ADD_imm_T3 = 0xF100,

OP_ADD_S_imm_T3 = 0xF110,

OP_CMN_imm = 0xF110,

OP_ADC_imm = 0xF140,

OP_SUB_imm_T3 = 0xF1A0,

OP_SUB_S_imm_T3 = 0xF1B0,

OP_CMP_imm_T2 = 0xF1B0,

OP_RSB_imm_T2 = 0xF1C0,

OP_RSB_S_imm_T2 = 0xF1D0,

OP_ADD_imm_T4 = 0xF200,

OP_MOV_imm_T3 = 0xF240,

OP_SUB_imm_T4 = 0xF2A0,

OP_MOVT = 0xF2C0,

OP_UBFX_T1 = 0xF3C0,

OP_NOP_T2a = 0xF3AF,

OP_DMB_T1a = 0xF3BF,

OP_STRB_imm_T3 = 0xF800,

OP_STRB_reg_T2 = 0xF800,

OP_LDRB_imm_T3 = 0xF810,

OP_LDRB_reg_T2 = 0xF810,

OP_STRH_imm_T3 = 0xF820,

OP_STRH_reg_T2 = 0xF820,

OP_LDRH_reg_T2 = 0xF830,

OP_LDRH_imm_T3 = 0xF830,

OP_STR_imm_T4 = 0xF840,

OP_STR_reg_T2 = 0xF840,

OP_LDR_imm_T4 = 0xF850,

OP_LDR_reg_T2 = 0xF850,

OP_STRB_imm_T2 = 0xF880,

OP_LDRB_imm_T2 = 0xF890,

OP_STRH_imm_T2 = 0xF8A0,

OP_LDRH_imm_T2 = 0xF8B0,

OP_STR_imm_T3 = 0xF8C0,

OP_LDR_imm_T3 = 0xF8D0,

OP_LDRSB_imm_T2 = 0xF910,

OP_LDRSB_reg_T2 = 0xF910,

OP_LDRSH_imm_T2 = 0xF930,

OP_LDRSH_reg_T2 = 0xF930,

OP_LDRSB_imm_T1 = 0xF990,

OP_LDRSH_imm_T1 = 0xF9B0,

OP_LSL_reg_T2 = 0xFA00,

OP_SXTH_T2 = 0xFA0F,

OP_UXTH_T2 = 0xFA1F,

OP_SXTB_T2 = 0xFA4F,

OP_UXTB_T2 = 0xFA5F,

OP_LSR_reg_T2 = 0xFA20,

OP_ASR_reg_T2 = 0xFA40,

OP_ROR_reg_T2 = 0xFA60,

OP_RBIT = 0xFA90,

OP_CLZ = 0xFAB0,

OP_SMULL_T1 = 0xFB80,

OP_UMULL_T1 = 0xFBA0,

#if HAVE(ARM_IDIV_INSTRUCTIONS)

OP_SDIV_T1 = 0xFB90,

OP_UDIV_T1 = 0xFBB0,

#endif

OP_MRS_T1 = 0xF3EF,

} OpcodeID1;

typedef enum {

OP_VAND_T1b = 0x0010,

OP_VORR_T1b = 0x0010,

OP_VADD_T2b = 0x0A00,

OP_VDIVb = 0x0A00,

OP_FLDSb = 0x0A00,

OP_VLDRb = 0x0A00,

OP_VMOV_IMM_T2b = 0x0A00,

OP_VMOV_T2b = 0x0A40,

OP_VMUL_T2b = 0x0A00,

OP_FSTSb = 0x0A00,

OP_VSTRb = 0x0A00,

OP_VMOV_StoCb = 0x0A10,

OP_VMOV_CtoSb = 0x0A10,

OP_VMOV_DtoCb = 0x0A10,

OP_VMOV_CtoDb = 0x0A10,

OP_VMRSb = 0x0A10,

OP_VABS_T2b = 0x0A40,

OP_VCMPb = 0x0A40,

OP_VCVT_FPIVFPb = 0x0A40,

OP_VNEG_T2b = 0x0A40,

OP_VSUB_T2b = 0x0A40,

OP_VSQRT_T1b = 0x0A40,

OP_VCVTSD_T1b = 0x0A40,

OP_VCVTDS_T1b = 0x0A40,

OP_VSTMIAb = 0x0B00,

OP_VLDMIAb = 0x0B00,

OP_NOP_T2b = 0x8000,

OP_DMB_SY_T1b = 0x8F5F,

OP_DMB_ISHST_T1b = 0x8F5A,

OP_DMB_ISH_T1b = 0x8F5B,

OP_B_T3b = 0x8000,

OP_B_T4b = 0x9000,

OP_BL_T4b = 0xD000,

} OpcodeID2;

struct FourFours {

FourFours(unsigned f3, unsigned f2, unsigned f1, unsigned f0)

{

m_u.f0 = f0;

m_u.f1 = f1;

m_u.f2 = f2;

m_u.f3 = f3;

}

union {

unsigned value;

struct {

unsigned f0 : 4;

unsigned f1 : 4;

unsigned f2 : 4;

unsigned f3 : 4;

};

} m_u;

};

enum class BranchWithLink : bool {

No = false,

Yes = true

};

class ARMInstructionFormatter;

// false means else!

static bool ifThenElseConditionBit(Condition condition, bool isIf)

{

return isIf ? (condition & 1) : !(condition & 1);

}

static uint8_t ifThenElse(Condition condition, bool inst2if, bool inst3if, bool inst4if)

{

int mask = (ifThenElseConditionBit(condition, inst2if) << 3)

| (ifThenElseConditionBit(condition, inst3if) << 2)

| (ifThenElseConditionBit(condition, inst4if) << 1)

| 1;

ASSERT((condition != ConditionAL) || !(mask & (mask - 1)));

return (condition << 4) | mask;

}

static uint8_t ifThenElse(Condition condition, bool inst2if, bool inst3if)

{

int mask = (ifThenElseConditionBit(condition, inst2if) << 3)

| (ifThenElseConditionBit(condition, inst3if) << 2)

| 2;

ASSERT((condition != ConditionAL) || !(mask & (mask - 1)));

return (condition << 4) | mask;

}

static uint8_t ifThenElse(Condition condition, bool inst2if)

{

int mask = (ifThenElseConditionBit(condition, inst2if) << 3)

| 4;

ASSERT((condition != ConditionAL) || !(mask & (mask - 1)));

return (condition << 4) | mask;

}

static uint8_t ifThenElse(Condition condition)

{

int mask = 8;

return (condition << 4) | mask;

}

void adc(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

// Rd can only be SP if Rn is also SP.

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(imm.isEncodedImm());

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADC_imm, rn, rd, imm);

}

void adc(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift = ShiftTypeAndAmount { })

{

// Rd can only be SP if Rn is also SP.

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_ADC_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

void add(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

// Rd can only be SP if Rn is also SP.

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(imm.isValid());

if (rn == ARMRegisters::sp && imm.isUInt16()) {

ASSERT(!(imm.getUInt16() & 3));

if (!(rd & 8) && imm.isUInt10()) {

m_formatter.oneWordOp5Reg3Imm8(OP_ADD_SP_imm_T1, rd, static_cast<uint8_t>(imm.getUInt10() >> 2));

return;

} else if ((rd == ARMRegisters::sp) && imm.isUInt9()) {

m_formatter.oneWordOp9Imm7(OP_ADD_SP_imm_T2, static_cast<uint8_t>(imm.getUInt9() >> 2));

return;

}

} else if (!((rd | rn) & 8)) {

if (imm.isUInt3()) {

m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_imm_T1, (RegisterID)imm.getUInt3(), rn, rd);

return;

} else if ((rd == rn) && imm.isUInt8()) {

m_formatter.oneWordOp5Reg3Imm8(OP_ADD_imm_T2, rd, imm.getUInt8());

return;

}

}

if (imm.isEncodedImm())

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADD_imm_T3, rn, rd, imm);

else {

ASSERT(imm.isUInt12());

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADD_imm_T4, rn, rd, imm);

}

}

ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)

{

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_ADD_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

// NOTE: In an IT block, add doesn't modify the flags register.

ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm)

{

if (rd == ARMRegisters::sp && rd != rn) {

mov(rd, rn);

rn = rd;

}

if (rd == rn)

m_formatter.oneWordOp8RegReg143(OP_ADD_reg_T2, rm, rd);

else if (rd == rm)

m_formatter.oneWordOp8RegReg143(OP_ADD_reg_T2, rn, rd);

else if (!((rd | rn | rm) & 8))

m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_reg_T1, rm, rn, rd);

else

add(rd, rn, rm, ShiftTypeAndAmount());

}

// Not allowed in an IT (if then) block.

ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

// Rd can only be SP if Rn is also SP.

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(imm.isEncodedImm());

if (!((rd | rn) & 8)) {

if (imm.isUInt3()) {

m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_imm_T1, (RegisterID)imm.getUInt3(), rn, rd);

return;

} else if ((rd == rn) && imm.isUInt8()) {

m_formatter.oneWordOp5Reg3Imm8(OP_ADD_imm_T2, rd, imm.getUInt8());

return;

}

}

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_ADD_S_imm_T3, rn, rd, imm);

}

// Not allowed in an IT (if then) block?

ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)

{

ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));

ASSERT(rd != ARMRegisters::pc);

ASSERT(rn != ARMRegisters::pc);

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_ADD_S_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

// Not allowed in an IT (if then) block.

ALWAYS_INLINE void add_S(RegisterID rd, RegisterID rn, RegisterID rm)

{

if (!((rd | rn | rm) & 8))

m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_reg_T1, rm, rn, rd);

else

add_S(rd, rn, rm, ShiftTypeAndAmount());

}

ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(imm.isEncodedImm());

m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_AND_imm_T1, rn, rd, imm);

}

ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_AND_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

ALWAYS_INLINE void ARM_and(RegisterID rd, RegisterID rn, RegisterID rm)

{

if ((rd == rn) && !((rd | rm) & 8))

m_formatter.oneWordOp10Reg3Reg3(OP_AND_reg_T1, rm, rd);

else if ((rd == rm) && !((rd | rn) & 8))

m_formatter.oneWordOp10Reg3Reg3(OP_AND_reg_T1, rn, rd);

else

ARM_and(rd, rn, rm, ShiftTypeAndAmount());

}

ALWAYS_INLINE void asr(RegisterID rd, RegisterID rm, int32_t shiftAmount)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rm));

ShiftTypeAndAmount shift(SRType_ASR, shiftAmount);

m_formatter.twoWordOp16FourFours(OP_ASR_imm_T1, FourFours(shift.hi4(), rd, shift.lo4(), rm));

}

ALWAYS_INLINE void asr(RegisterID rd, RegisterID rn, RegisterID rm)

{

ASSERT(!BadReg(rd));

ASSERT(!BadReg(rn));

ASSERT(!BadReg(rm));

m_formatter.twoWordOp12Reg4FourFours(OP_ASR_reg_T2, rn, FourFours(0xf, rd, 0, rm));

}

// Only allowed in IT (if then) block if last instruction.

ALWAYS_INLINE AssemblerLabel b()

{

m_formatter.twoWordOp16Op16(OP_B_T4a, OP_B_T4b);

return m_formatter.label();

}

// Only allowed in IT (if then) block if last instruction.

ALWAYS_INLINE AssemblerLabel bl()

{

m_formatter.twoWordOp16Op16(OP_BL_T4a, OP_BL_T4b);

return m_formatter.label();

}

// Only allowed in IT (if then) block if last instruction.

ALWAYS_INLINE AssemblerLabel blx(RegisterID rm)

{

ASSERT(rm != ARMRegisters::pc);

m_formatter.oneWordOp8RegReg143(OP_BLX, rm, (RegisterID)8);

return m_formatter.label();

}

// Only allowed in IT (if then) block if last instruction.

ALWAYS_INLINE AssemblerLabel bx(RegisterID rm)

{

m_formatter.oneWordOp8RegReg143(OP_BX, rm, (RegisterID)0);

return m_formatter.label();

}

ALWAYS_INLINE void bic(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)