https://riscv.org/about/
https://en.wikipedia.org/wiki/RISC-V

Description:

RISC-V is a relatively new open standard instruction set architecture (ISA). With only 40 base instructions it is rather simple compared to x86 or ARM assembly, and thus presents an unique challenge compared to the already existing assembly language.

For code golf it would probably make sense to use the RV32GC variant (32-bit base with the "GC" set of extensions) which includes support for floating point arithmetic, multiplication/division, compressed instructions, etc in addition to the 40 instructions included in base. The scoring could make sense both in (compiled) bytes and source code characters.

It could be implemented by running the qemu-system-riscv64 emulator inside docker (example image: https://hub.docker.com/r/davidburela/riscv-emulator).