hypervisor: mshv: Complete guest boot support for ARM64#7055
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jinankjain merged 9 commits intocloud-hypervisor:mainfrom May 9, 2025
Merged
hypervisor: mshv: Complete guest boot support for ARM64#7055jinankjain merged 9 commits intocloud-hypervisor:mainfrom
jinankjain merged 9 commits intocloud-hypervisor:mainfrom
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Currently PPI interrupt ID are hardcoded as numbers, it would be ideal to define them as constants and could be reused in other parts of the hypervisor crate. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Since this would be used in other places inside the hypervisor and hypervisor crate cannot take a dependency on arch crate, as that creates cyclic dependency. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
liuw
reviewed
May 8, 2025
For ARM64 guests we need to set three important partition property: 1) PPI interrupt ID for timer interrupt 2) PPI interrupt ID for PMU interrupts. 3) Hiding LPI support from the guest because MSHV does emulate ITS for the guest. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
For MSHV guests, we would need interrupt controller to be initialized before the VM gets initialized. This is because we are registering the base address of GIC distributor with MSHV as part of interrupt controller initialization workflow. And MSHV mandates that this property is set before we initialize the VM. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
This will satisfy the requirement of MSHV i.e., setting the GICD base address before initializing the VM. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
It just simplifies code and improves the code read-ability without much affecting the boot performance. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
It seems like address allocation has been spread into different files and different location for x86 vs ARM. This makes it hard to follow the code. Thus, unify it a single location which satisfies all the requirement. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Num SPI and Base SPI nodes should be added before the end node to be included in the device tree generation. Fixes: eac44e6 (arch: Extend FDT for GICv2M device for ARM64 on MSHV) Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
Currently a lot of functions are stubbed out with unimplemented feature tag. Add the missing implementation to successfully boot ARM64 guests on MSHV. Signed-off-by: Jinank Jain <jinankjain@microsoft.com>
liuw
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May 9, 2025
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@rbradford @likebreath It would be great if one of you could also take a look at this one? |
rbradford
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Code looks good overall with some potential nits.
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@rbradford Something changed in the CI getting this error: |
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I've fixed this. And it's running the job now - https://github.com/cloud-hypervisor/cloud-hypervisor/actions/runs/14931917110/job/41951078105 |
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This patch series contains the final set of patches required to boot ARM64 guests on MSHV.