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aarch64: implement ISLE lowering for bitselect.i128 (#14237)
* aarch64: implement ISLE lowering for bitselect.i128 This implements the missing bitselect lowering rule for i128 on AArch64 using pair-wise 64-bit word operations (and, bic, orr). Fixes #5198 * aarch64: convert bitselect-i128 test to precise-output, enable runtest
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‎cranelift/codegen/src/isa/aarch64/lower.isle‎

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(tmp2 Reg (bic ty y c)))
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(orr ty tmp1 tmp2)))
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(attr rule bitselect_i128 (tag i128))
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(rule bitselect_i128 2 (lower (bitselect $I128 c x y))
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(let ((c ValueRegs (put_in_regs c))
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(x ValueRegs (put_in_regs x))
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(y ValueRegs (put_in_regs y))
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(c_lo Reg (value_regs_get c 0))
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(c_hi Reg (value_regs_get c 1))
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(x_lo Reg (value_regs_get x 0))
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(x_hi Reg (value_regs_get x 1))
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(y_lo Reg (value_regs_get y 0))
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(y_hi Reg (value_regs_get y 1))
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(tmp1_lo Reg (and_reg $I64 x_lo c_lo))
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(tmp1_hi Reg (and_reg $I64 x_hi c_hi))
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(tmp2_lo Reg (bic $I64 y_lo c_lo))
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(tmp2_hi Reg (bic $I64 y_hi c_hi))
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(res_lo Reg (orr $I64 tmp1_lo tmp2_lo))
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(res_hi Reg (orr $I64 tmp1_hi tmp2_hi)))
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(value_regs res_lo res_hi)))
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(rule 1 (lower (bitselect (ty_vec128 ty) c x y))
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(bsl ty c x y))
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‎cranelift/filetests/filetests/isa/aarch64/bitselect-i128.clif‎

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test compile precise-output
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set unwind_info=false
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target aarch64
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function %f0(i128, i128, i128) -> i128 {
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block0(v0: i128, v1: i128, v2: i128):
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v3 = bitselect v0, v1, v2
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return v3
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}
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; VCode:
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; block0:
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; and x7, x2, x0
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; and x9, x3, x1
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; bic x11, x4, x0
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; bic x13, x5, x1
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; orr x0, x7, x11
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; orr x1, x9, x13
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; and x7, x2, x0
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; and x9, x3, x1
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; bic x11, x4, x0
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; bic x13, x5, x1
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; orr x0, x7, x11
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; orr x1, x9, x13
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; ret

‎cranelift/filetests/filetests/runtests/i128-bitselect.clif‎

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test run
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set opt_level=none
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set enable_llvm_abi_extensions=true
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target aarch64
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target x86_64
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set enable_multi_ret_implicit_sret
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target s390x

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