feat(aot/riscv): Enhance PCREL relocation handling with HI20/LO12 cac…#4777
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no1wudi wants to merge 1 commit intobytecodealliance:mainfrom
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feat(aot/riscv): Enhance PCREL relocation handling with HI20/LO12 cac…#4777no1wudi wants to merge 1 commit intobytecodealliance:mainfrom
no1wudi wants to merge 1 commit intobytecodealliance:mainfrom
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no1wudi
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TianlongLiang,
loganek,
lum1n0us and
yamt
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…hing
Implement proper R_RISCV_PCREL_HI20/R_RISCV_PCREL_LO12_{I,S} pairing
mechanism for RISC-V AOT relocation processing.
Changes:
- Add PCREL cache to match HI20 relocations with their corresponding LO12
entries, ensuring correct PC-relative offset computation
- Export aot_reloc_reset_cache() to clear cache state
- Implement proper LO12 relocation handling that uses cached HI20 offset
- Add overflow detection for PCREL cache to fail gracefully with error
- Add RV64 immediate validation for HI20 relocations
This enhances the RISC-V relocation system to correctly handle PC-relative
relocations used by LLVM for position-independent code generation.
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…hing
Implement proper R_RISCV_PCREL_HI20/R_RISCV_PCREL_LO12_{I,S} pairing mechanism for RISC-V AOT relocation processing.
Changes:
This enhances the RISC-V relocation system to correctly handle PC-relative relocations used by LLVM for position-independent code generation.