rk3568: add 51.2MHz PLL rate for HDMI#9477
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📝 WalkthroughWalkthroughTwo patches add a 51.2 MHz PLL rate entry to the Rockchip RK3568 clock driver's rate table across kernel versions 6.18 and 6.19. Each patch inserts an identical initializer (RK3036_PLL_RATE(51200000, 1, 64, 6, 5, 1, 0)) into the rk3568_pll_rates array to enable HDMI display support at 1024x600@60Hz resolution. Changes
Estimated code review effort🎯 2 (Simple) | ⏱️ ~10 minutes Poem
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You're aware that the patch at the moment only applies to |
this is probably a symptom of "this actually needs to be sent upstream" |
So, what should I do? |
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Either you add for 6.19 which I will then take over to 7.0 via rebase or you leave this PR as it is and do another one later once the version bump has been merged. Your call. Edit: I just realized you did not put your patch into the actual archive. Well since 6.18 is |
Placed patch to 6.18 & 6.19 folders. |
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✅ This PR has been reviewed and approved — all set for merge! |
Description
The RK3568/RK3566 mainline clock driver (
drivers/clk/rockchip/clk-rk3568.c) uses a fixed PLL rate table for all PLLs including HPLL, which drives the HDMI reference clock. The table is missing a 51.2 MHz entry — the pixel clock required by 1024x600@60Hz displays such as the BigTreeTech HDMI7.Without this rate,
dw_hdmi_rockchip_mode_valid()rejects every mode becauseclk_round_rate()can only return frequencies from the table, and the nearest entries (74.25 MHz and 33.3 MHz) are 45% and 35% off — far outside the 0.1% tolerance. Result: black screen,[drm] Cannot find any crtc or sizesin dmesg.Fix: add
RK3036_PLL_RATE(51200000, 1, 64, 6, 5, 1, 0)tork3568_pll_rates[].PLL math: 24 MHz * 64 / (6 * 5) = 51.2 MHz exactly, VCO = 1536 MHz.
How Has This Been Tested?
./compile.sh kernel BOARD=bigtreetech-cb2 BRANCH=edge|current RELEASE=trixiecat /sys/class/drm/card0-HDMI-A-1/modesshows1024x600Checklist:
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