This repo contains Verilog design and testbench files for a PWM signal generation (duty cycle varies with amplitude of pre-computed sine wave) targetted for Zync Zedboard:
An online sine wave generator produces a lookup table vector which when plotted (in MATLAB) provides the following sine wave cycle with 256 levels:
The above pre-computed sine wave is programmed as an LUT in the source files and a PWM signal is generated whose duty cycle varies with the sine wave's amplitude:
The PWM signal is generated on the JB7 pin of the Zedboard:
The design also offers the use of an Integrated Logic Analyzer (ILA) that can tap the sinusoidal and PWM signals:
