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X86Assembler.h
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7475 lines (6466 loc) · 290 KB
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/*
* Copyright (C) 2008-2023 Apple Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#pragma once
#include <wtf/Platform.h>
#if ENABLE(ASSEMBLER) && CPU(X86_64)
#include <JavaScriptCore/AssemblerBuffer.h>
#include <JavaScriptCore/AssemblerCommon.h>
#include <JavaScriptCore/JITCompilationEffort.h>
#include <JavaScriptCore/RegisterInfo.h>
#include <JavaScriptCore/SIMDInfo.h>
#include <limits.h>
#include <stdint.h>
#include <wtf/Assertions.h>
#include <wtf/Vector.h>
namespace JSC {
inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(signed char)value; }
namespace RegisterNames {
#define REGISTER_ID(id, name, res, cs) id,
typedef enum : int8_t {
FOR_EACH_GP_REGISTER(REGISTER_ID)
InvalidGPRReg = -1,
} RegisterID;
typedef enum : int8_t {
FOR_EACH_SP_REGISTER(REGISTER_ID)
} SPRegisterID;
typedef enum : int8_t {
FOR_EACH_FP_REGISTER(REGISTER_ID)
InvalidFPRReg = -1,
} XMMRegisterID;
#undef REGISTER_ID
} // namespace X86Registers
class X86Assembler {
public:
typedef X86Registers::RegisterID RegisterID;
static constexpr RegisterID firstRegister() { return X86Registers::eax; }
static constexpr RegisterID lastRegister()
{
return X86Registers::r15;
}
static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; }
typedef X86Registers::SPRegisterID SPRegisterID;
static constexpr SPRegisterID firstSPRegister() { return X86Registers::eip; }
static constexpr SPRegisterID lastSPRegister() { return X86Registers::eflags; }
static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; }
typedef X86Registers::XMMRegisterID XMMRegisterID;
typedef XMMRegisterID FPRegisterID;
static constexpr FPRegisterID firstFPRegister() { return X86Registers::xmm0; }
static constexpr FPRegisterID lastFPRegister()
{
return X86Registers::xmm15;
}
static constexpr unsigned numberOfFPRegisters() { return lastFPRegister() - firstFPRegister() + 1; }
static ASCIILiteral gprName(RegisterID id)
{
ASSERT(id >= firstRegister() && id <= lastRegister());
static constexpr ASCIILiteral nameForRegister[numberOfRegisters()] = {
#define REGISTER_NAME(id, name, res, cs) name,
FOR_EACH_GP_REGISTER(REGISTER_NAME)
#undef REGISTER_NAME
};
return nameForRegister[id];
}
static ASCIILiteral sprName(SPRegisterID id)
{
ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
static constexpr ASCIILiteral const nameForRegister[numberOfSPRegisters()] = {
#define REGISTER_NAME(id, name, res, cs) name,
FOR_EACH_SP_REGISTER(REGISTER_NAME)
#undef REGISTER_NAME
};
return nameForRegister[id];
}
static ASCIILiteral fprName(FPRegisterID reg)
{
ASSERT(reg >= firstFPRegister() && reg <= lastFPRegister());
static constexpr ASCIILiteral nameForRegister[numberOfFPRegisters()] = {
#define REGISTER_NAME(id, name, res, cs) name,
FOR_EACH_FP_REGISTER(REGISTER_NAME)
#undef REGISTER_NAME
};
return nameForRegister[reg];
}
typedef enum {
ConditionO,
ConditionNO,
ConditionB,
ConditionAE,
ConditionE,
ConditionNE,
ConditionBE,
ConditionA,
ConditionS,
ConditionNS,
ConditionP,
ConditionNP,
ConditionL,
ConditionGE,
ConditionLE,
ConditionG,
ConditionC = ConditionB,
ConditionNC = ConditionAE,
} Condition;
private:
// OneByteOpcodeID defines the bytecode for 1 byte instruction. It also contains the prefixes
// for two bytes instructions.
// TwoByteOpcodeID, ThreeByteOpcodeID define the opcodes for the multibytes instructions.
//
// The encoding for each instruction can be found in the Intel Architecture Manual in the appendix
// "Opcode Map."
//
// Each opcode can have a suffix describing the type of argument. The full list of suffixes is
// in the "Key to Abbreviations" section of the "Opcode Map".
// The most common argument types are:
// -E: The argument is either a GPR or a memory address.
// -G: The argument is a GPR.
// -I: The argument is an immediate.
// The most common sizes are:
// -v: 32 or 64bit depending on the operand-size attribute.
// -z: 32bit in both 32bit and 64bit mode. Common for immediate values.
typedef enum {
OP_ADD_EbGb = 0x00,
PRE_SSE_00 = 0x00,
OP_ADD_EvGv = 0x01,
OP_ADD_GvEv = 0x03,
OP_ADD_EAXIv = 0x05,
OP_OR_EvGb = 0x08,
OP_OR_EvGv = 0x09,
OP_OR_GvEv = 0x0B,
OP_OR_EAXIv = 0x0D,
OP_2BYTE_ESCAPE = 0x0F,
OP_AND_EvGb = 0x20,
OP_AND_EvGv = 0x21,
OP_AND_GvEv = 0x23,
OP_SUB_EvGb = 0x28,
OP_SUB_EvGv = 0x29,
OP_SUB_GvEv = 0x2B,
OP_SUB_EAXIv = 0x2D,
PRE_PREDICT_BRANCH_NOT_TAKEN = 0x2E,
OP_XOR_EvGb = 0x30,
OP_XOR_EvGv = 0x31,
OP_XOR_GvEv = 0x33,
OP_XOR_EAXIv = 0x35,
OP_CMP_EvGv = 0x39,
OP_CMP_GvEv = 0x3B,
OP_CMP_EAXIv = 0x3D,
PRE_REX = 0x40,
OP_PUSH_EAX = 0x50,
OP_POP_EAX = 0x58,
OP_MOVSXD_GvEv = 0x63,
PRE_GS = 0x65,
PRE_OPERAND_SIZE = 0x66,
PRE_SSE_66 = 0x66,
OP_PUSH_Iz = 0x68,
OP_IMUL_GvEvIz = 0x69,
OP_GROUP1_EbIb = 0x80,
OP_GROUP1_EvIz = 0x81,
OP_GROUP1_EvIb = 0x83,
OP_TEST_EbGb = 0x84,
OP_TEST_EvGv = 0x85,
OP_XCHG_EvGb = 0x86,
OP_XCHG_EvGv = 0x87,
OP_MOV_EbGb = 0x88,
OP_MOV_EvGv = 0x89,
OP_MOV_GvEv = 0x8B,
OP_LEA = 0x8D,
OP_GROUP1A_Ev = 0x8F,
OP_NOP = 0x90,
OP_XCHG_EAX = 0x90,
OP_PAUSE = 0x90,
OP_CDQ = 0x99,
OP_MOV_EAXOv = 0xA1,
OP_MOV_OvEAX = 0xA3,
OP_TEST_ALIb = 0xA8,
OP_TEST_EAXIv = 0xA9,
OP_MOV_EAXIv = 0xB8,
OP_GROUP2_EvIb = 0xC1,
OP_RET = 0xC3,
OP_GROUP11_EvIb = 0xC6,
OP_GROUP11_EvIz = 0xC7,
OP_INT3 = 0xCC,
OP_GROUP2_Ev1 = 0xD1,
OP_GROUP2_EvCL = 0xD3,
OP_ESCAPE_D9 = 0xD9,
OP_ESCAPE_DD = 0xDD,
OP_CALL_rel32 = 0xE8,
OP_JMP_rel32 = 0xE9,
PRE_LOCK = 0xF0,
PRE_SSE_F2 = 0xF2,
PRE_SSE_F3 = 0xF3,
OP_HLT = 0xF4,
OP_GROUP3_Eb = 0xF6,
OP_GROUP3_EbIb = 0xF6,
OP_GROUP3_Ev = 0xF7,
OP_GROUP3_EvIz = 0xF7, // OP_GROUP3_Ev has an immediate, when instruction is a test.
OP_GROUP5_Ev = 0xFF,
} OneByteOpcodeID;
typedef enum {
OP2_UD2 = 0xB,
OP2_MOVSD_VsdWsd = 0x10,
OP2_MOVUPS_VsdWsd = 0x10,
OP2_MOVSS_VsdWsd = 0x10,
OP2_MOVSD_WsdVsd = 0x11,
OP2_MOVUPS_WsdVsd = 0x11,
OP2_MOVSS_WsdVsd = 0x11,
OP2_MOVDDUP_VqWq = 0x12,
OP2_MOVHLPS_VqUq = 0x12,
OP2_MOVSLDUP_VqWq = 0x12,
OP2_UNPCKLPD_VpdWpd = 0x14,
OP2_UNPCKHPD_VpdWpd = 0x15,
OP2_MOVSHDUP_VqWq = 0x16,
OP2_MOVLHPS_VqUq = 0x16,
OP2_MOVAPD_VpdWpd = 0x28,
OP2_MOVAPS_VpsWps = 0x28,
OP2_MOVAPS_WpsVps = 0x29,
OP2_CVTSI2SS_VssEs = 0x2A,
OP2_CVTSI2SD_VsdEd = 0x2A,
OP2_CVTTSD2SI_GdWsd = 0x2C,
OP2_CVTTSS2SI_GdWsd = 0x2C,
OP2_UCOMISS_VssWss = 0x2E,
OP2_UCOMISD_VsdWsd = 0x2E,
OP2_RDTSC = 0x31,
OP2_3BYTE_ESCAPE_38 = 0x38,
OP2_3BYTE_ESCAPE_3A = 0x3A,
OP2_CMOVCC = 0x40,
OP2_MOVMSKPD_VdEd = 0x50,
OP2_SQRTSD_VsdWsd = 0x51,
OP2_SQRTSS_VssWss = 0x51,
OP2_ANDPS_VpsWps = 0x54,
OP2_ANDPD_VpdWpd = 0x54,
OP2_ANDNPS_VpsWps = 0x55,
OP2_ANDNPD_VpdWpd = 0x55,
OP2_ORPS_VpsWps = 0x56,
OP2_ORPD_VpdWpd = 0x56,
OP2_XORPS_VpsWps = 0x57,
OP2_XORPD_VpdWpd = 0x57,
OP2_ADDSD_VsdWsd = 0x58,
OP2_MULSD_VsdWsd = 0x59,
OP2_CVTSD2SS_VsdWsd = 0x5A,
OP2_CVTPS2PD_VsdWsd = 0x5A,
OP2_CVTSS2SD_VsdWsd = 0x5A,
OP2_CVTPD2PS_VsdWsd = 0x5A,
OP2_CVTDQ2PS_VsdWsd = 0x5B,
OP2_SUBSD_VsdWsd = 0x5C,
OP2_MINPS_VpsWps = 0x5D,
OP2_MINPD_VpdWpd = 0x5D,
OP2_DIVSD_VsdWsd = 0x5E,
OP2_MAXPS_VpsWps = 0x5F,
OP2_MAXPD_VpdWpd = 0x5F,
OP2_PUNPCKLBW_VdqWdq = 0x60,
OP2_PUNPCKLWD_VdqWdq = 0x61,
OP2_PUNPCKLDQ_VdqWdq = 0x62,
OP2_PACKSSWB_VdqWdq = 0x63,
OP2_PACKUSWB_VdqWdq = 0x67,
OP2_PUNPCKHBW_VdqWdq = 0x68,
OP2_PUNPCKHWD_VdqWdq = 0x69,
OP2_PUNPCKHDQ_VdqWdq = 0x6A,
OP2_PACKSSDW_VdqWdq = 0x6B,
OP2_PUNPCKLQDQ_VdqWdq = 0x6C,
OP2_PUNPCKHQDQ_VdqWdq = 0x6D,
OP2_MOVD_VdEd = 0x6E,
OP2_MOVQ_PqQq = 0x6E,
OP2_MOVDQA_VdqWdq = 0x6F,
OP2_PSHUFD_VdqWdqIb = 0x70,
OP2_PSHUFLW_VdqWdqIb = 0x70,
OP2_PSHUFHW_VdqWdqIb = 0x70,
OP2_PSLLW_UdqIb = 0x71,
OP2_PSRLW_UdqIb = 0x71,
OP2_PSRAW_UdqIb = 0x71,
OP2_PSLLD_UdqIb = 0x72,
OP2_PSRLD_UdqIb = 0x72,
OP2_PSRAD_UdqIb = 0x72,
OP2_PSLLQ_UdqIb = 0x73,
OP2_PSRLQ_UdqIb = 0x73,
OP2_VZEROUPPER = 0x77,
OP2_MOVD_EdVd = 0x7E,
OP2_MOVQ_QqPq = 0x7E,
OP2_JCC_rel32 = 0x80,
OP_SETCC = 0x90,
OP2_CPUID = 0xA2,
OP2_BT_EvEv = 0xA3,
OP2_3BYTE_ESCAPE_AE = 0xAE,
OP2_IMUL_GvEv = 0xAF,
OP2_CMPXCHGb = 0xB0,
OP2_CMPXCHG = 0xB1,
OP2_BTR = 0xB3,
OP2_MOVZX_GvEb = 0xB6,
OP2_POPCNT = 0xB8,
OP2_GROUP_BT_EvIb = 0xBA,
OP2_BSF = 0xBC,
OP2_TZCNT = 0xBC,
OP2_BSR = 0xBD,
OP2_LZCNT = 0xBD,
OP2_MOVSX_GvEb = 0xBE,
OP2_MOVZX_GvEw = 0xB7,
OP2_MOVSX_GvEw = 0xBF,
OP2_XADDb = 0xC0,
OP2_XADD = 0xC1,
OP2_PINSRW_VdqRdqp = 0xC4,
OP2_PEXTRW_GdUdIb = 0xC5,
OP2_SHUFPD_VpdWpdIb = 0xC6,
OP2_SHUFPS_VpdWpdIb = 0xC6,
OP2_BSWAP = 0xC8,
OP2_PSUBUSB_VdqWdq = 0xD8,
OP2_PSUBUSW_VdqWdq = 0xD9,
OP2_VPAND_VxHxWx = 0xDB,
OP2_PADDUSB_VdqWdq = 0xDC,
OP2_PADDUSW_VdqWdq = 0xDD,
OP2_PAVGB_VdqWdq = 0xE0,
OP2_PAVGW_VdqWdq = 0xE3,
OP2_PMULHUW_VdqWdq = 0xE4,
OP2_PMULHW_VdqWdq = 0xE5,
OP2_CVTDQ2PD_VdqWdq = 0xE6,
OP2_CVTDPD2DQ_VdqWdq = 0xE6,
OP2_PSUBSB_VdqWdq = 0xE8,
OP2_PSUBSW_VdqWdq = 0xE9,
OP2_POR_VdqWdq = 0XEB,
OP2_PADDSB_VdqWdq = 0xEC,
OP2_PADDSW_VdqWdq = 0xED,
OP2_PXOR_VdqWdq = 0xEF,
OP2_PADDB_VdqWdq = 0xFC,
OP2_PADDW_VdqWdq = 0xFD,
OP2_PADDD_VdqWdq = 0xFE,
OP2_PADDQ_VdqWdq = 0xD4,
OP2_PSUBB_VdqWdq = 0xF8,
OP2_PSUBW_VdqWdq = 0xF9,
OP2_PSUBD_VdqWdq = 0xFA,
OP2_PSUBQ_VdqWdq = 0xFB,
OP2_PMULLW_VdqWdq = 0xD5,
OP2_PMOVMSKB_GdqpUdq = 0xD7,
OP2_ADDPS_VpsWps = 0x58,
OP2_ADDPD_VpdWpd = 0x58,
OP2_SUBPS_VpsWps = 0x5C,
OP2_SUBPD_VpdWpd = 0x5C,
OP2_MULPS_VpsWps = 0x59,
OP2_MULPD_VpdWpd = 0x59,
OP2_DIVPS_VpsWps = 0x5E,
OP2_DIVPD_VpdWpd = 0x5E,
OP2_DIVSS_VpsWps = 0x5E,
OP2_SQRTPS_VpsWps = 0x51,
OP2_SQRTPD_VpdWpd = 0x51,
OP2_PMADDWD_VdqWdq = 0xF5,
OP2_VPSLLD_VxHxWx = 0x72,
OP2_PCMPEQB_VdqWdq = 0x74,
OP2_PCMPEQW_VdqWdq = 0x75,
OP2_PCMPEQD_VdqWdq = 0x76,
OP2_PCMPGTB_VdqWdq = 0x64,
OP2_PCMPGTW_VdqWdq = 0x65,
OP2_PCMPGTD_VdqWdq = 0x66,
OP2_CMPPS_VpsWpsIb = 0xC2,
OP2_CMPPD_VpdWpdIb = 0xC2,
OP2_PMAXSW_VdqWdq = 0xEE,
OP2_PMAXUB_VdqWdq = 0xDE,
OP2_PMINSW_VdqWdq = 0xEA,
OP2_PMINUB_VdqWdq = 0xDA,
OP2_PSRLW_VdqWdq = 0xD1,
OP2_PSRLD_VdqWdq = 0xD2,
OP2_PSRLQ_VdqWdq = 0xD3,
OP2_PSRAW_VdqWdq = 0xE1,
OP2_PSRAD_VdqWdq = 0xE2,
OP2_PSLLW_VdqWdq = 0xF1,
OP2_PSLLD_VdqWdq = 0xF2,
OP2_PSLLQ_VdqWdq = 0xF3,
OP2_PMULUDQ_VdqWdq = 0xF4,
OP2_PMOVMSKB_EqWdq = 0xD7,
OP2_MOVMSKPS_EqWps = 0x50,
OP2_MOVMSKPD_EqWpd = 0x50,
} TwoByteOpcodeID;
typedef enum {
OP3_PSHUFB_VdqWdq = 0x00,
OP3_PMADDUBSW_VpdWpd = 0x04,
OP3_ROUNDPD_MbVdqIb = 0x09,
OP3_ROUNDSS_VssWssIb = 0x0A,
OP3_ROUNDSD_VsdWsdIb = 0x0B,
OP3_VPBLENDW_VxHxWxIb = 0x0E,
OP3_PALIGNR_VdqWdqIb = 0x0F,
OP3_PEXTRB_MbVdqIb = 0x14,
OP3_PEXTRW_MwVdqIb = 0x15,
OP3_PEXTRD_EyVdqIb = 0x16,
OP3_PEXTRQ_EyVdqIb = 0x16,
OP3_EXTRACTPS_EdVdqIb = 0x17,
OP3_VBROADCASTSS_VxWd = 0x18,
OP3_VBROADCASTSD_VxWd = 0x19,
OP3_PABSB_VdqWdq = 0x1C,
OP3_PABSW_VdqWdq = 0x1D,
OP3_PABSD_VdqWdq = 0x1E,
OP3_VPMOVSXBW_VxUx = 0x20,
OP3_PINSRB_VdqRdqpIb = 0x20,
OP3_INSERTPS_VpsUpsIb = 0x21,
OP3_PINSRD_VdqEdIb = 0x22,
OP3_PINSRQ_VdqEqbIb = 0x22,
OP3_VPMOVSXWD_VxUx = 0x23,
OP3_VPMOVSXDQ_VxUx = 0x25,
OP3_PMULDQ_VdqWdq = 0x28,
OP3_VPACKUSDW_VxHxWx = 0x2B,
OP3_VPMOVZXBW_VxUx = 0x30,
OP3_VPMOVZXWD_VxUx = 0x33,
OP3_VPMOVZXDQ_VxUx = 0x35,
OP3_BLENDVPD_VpdWpdXMM0 = 0x4B,
OP3_VPBROADCASTD_VxUx = 0x58,
OP3_VPBROADCASTQ_VxUx = 0x59,
OP3_VPBROADCASTB_VxUx = 0x78,
OP3_VPBROADCASTW_VxUx = 0x79,
OP3_LFENCE = 0xE8,
OP3_MFENCE = 0xF0,
OP3_SFENCE = 0xF8,
OP3_ROUNDPS_VpsWpsIb = 0x08,
OP3_ROUNDPD_VpdWpdIb = 0x09,
OP3_PMULLD_VdqWdq = 0x40,
OP3_PCMPEQQ_VdqWdq = 0x29,
OP3_PCMPGTQ_VdqWdq = 0x37,
OP3_PMINSB_VdqWdq = 0x38,
OP3_PMINSD_VdqWdq = 0x39,
OP3_PMINUW_VdqWdq = 0x3A,
OP3_PMINUD_VdqWdq = 0x3B,
OP3_PMAXSB_VdqWdq = 0x3C,
OP3_PMAXSD_VdqWdq = 0x3D,
OP3_PMAXUW_VdqWdq = 0x3E,
OP3_PMAXUD_VdqWdq = 0x3F,
OP3_PTEST_VdqWdq = 0x17,
} ThreeByteOpcodeID;
enum class VexPrefix : uint8_t {
TwoBytes = 0xC5,
ThreeBytes = 0xC4,
};
// Bits[4:0] of the 3-byte VEX byte 1 encode an implied leading opcode byte (0F, 0F 38, or 0F 3A).
// Several bits are reserved for future use and will #UD unless 0.
enum class VexImpliedBytes : uint8_t {
TwoBytesOp = 0b01, // 0F
ThreeBytesOp38 = 0b10, // 0F 38
ThreeBytesOp3A = 0b11, // 0F 3A
};
enum class VexW : uint8_t {
W0 = 0,
W1 = 1,
};
TwoByteOpcodeID cmovcc(Condition cond)
{
return (TwoByteOpcodeID)(OP2_CMOVCC + static_cast<TwoByteOpcodeID>(cond));
}
TwoByteOpcodeID jccRel32(Condition cond)
{
return (TwoByteOpcodeID)(OP2_JCC_rel32 + static_cast<TwoByteOpcodeID>(cond));
}
TwoByteOpcodeID setccOpcode(Condition cond)
{
return (TwoByteOpcodeID)(OP_SETCC + static_cast<TwoByteOpcodeID>(cond));
}
typedef enum {
GROUP1_OP_ADD = 0,
GROUP1_OP_OR = 1,
GROUP1_OP_ADC = 2,
GROUP1_OP_AND = 4,
GROUP1_OP_SUB = 5,
GROUP1_OP_XOR = 6,
GROUP1_OP_CMP = 7,
GROUP1A_OP_POP = 0,
GROUP2_OP_ROL = 0,
GROUP2_OP_ROR = 1,
GROUP2_OP_RCL = 2,
GROUP2_OP_RCR = 3,
GROUP2_OP_SHL = 4,
GROUP2_OP_SHR = 5,
GROUP2_OP_SAR = 7,
GROUP3_OP_TEST = 0,
GROUP3_OP_NOT = 2,
GROUP3_OP_NEG = 3,
GROUP3_OP_MUL = 4,
GROUP3_OP_IMUL = 5,
GROUP3_OP_DIV = 6,
GROUP3_OP_IDIV = 7,
GROUP5_OP_CALLN = 2,
GROUP5_OP_JMPN = 4,
GROUP5_OP_PUSH = 6,
GROUP11_MOV = 0,
GROUP14_OP_PSLLD = 6,
GROUP14_OP_PSLLQ = 6,
GROUP14_OP_PSRAQ = 4,
GROUP14_OP_PSRLQ = 2,
ESCAPE_D9_FSTP_singleReal = 3,
ESCAPE_DD_FSTP_doubleReal = 3,
GROUP_BT_OP_BT = 4,
} GroupOpcodeID;
class X86InstructionFormatter;
public:
X86Assembler()
: m_indexOfLastWatchpoint(INT_MIN)
, m_indexOfTailOfLastWatchpoint(INT_MIN)
{
}
AssemblerBuffer& buffer() LIFETIME_BOUND { return m_formatter.m_buffer; }
// Stack operations:
void push_r(RegisterID reg)
{
m_formatter.oneByteOp(OP_PUSH_EAX, reg);
}
void pop_r(RegisterID reg)
{
m_formatter.oneByteOp(OP_POP_EAX, reg);
}
void push_i32(int imm)
{
m_formatter.oneByteOp(OP_PUSH_Iz);
m_formatter.immediate32(imm);
}
void push_m(int offset, RegisterID base)
{
m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_PUSH, base, offset);
}
void pop_m(int offset, RegisterID base)
{
m_formatter.oneByteOp(OP_GROUP1A_Ev, GROUP1A_OP_POP, base, offset);
}
// Arithmetic operations:
void addl_rr(RegisterID src, RegisterID dst)
{
m_formatter.oneByteOp(OP_ADD_EvGv, src, dst);
}
void addl_mr(int offset, RegisterID base, RegisterID dst)
{
m_formatter.oneByteOp(OP_ADD_GvEv, dst, base, offset);
}
void addl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
{
m_formatter.oneByteOp(OP_ADD_GvEv, dst, base, index, scale, offset);
}
void addl_rm(RegisterID src, int offset, RegisterID base)
{
m_formatter.oneByteOp(OP_ADD_EvGv, src, base, offset);
}
void addl_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp(OP_ADD_EvGv, src, base, index, scale, offset);
}
void addb_rm(RegisterID src, int offset, RegisterID base)
{
m_formatter.oneByteOp8(OP_ADD_EbGb, src, base, offset);
}
void addb_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp8(OP_ADD_EbGb, src, base, index, scale, offset);
}
void addw_rm(RegisterID src, int offset, RegisterID base)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
m_formatter.oneByteOp8(OP_ADD_EvGv, src, base, offset);
}
void addw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
m_formatter.oneByteOp8(OP_ADD_EvGv, src, base, index, scale, offset);
}
void addl_ir(int imm, RegisterID dst)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst);
m_formatter.immediate8(imm);
} else {
if (dst == X86Registers::eax)
m_formatter.oneByteOp(OP_ADD_EAXIv);
else
m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);
m_formatter.immediate32(imm);
}
}
void addl_im(int imm, int offset, RegisterID base)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);
m_formatter.immediate32(imm);
}
}
void addl_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, index, scale, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, index, scale, offset);
m_formatter.immediate32(imm);
}
}
void addb_im(int imm, int offset, RegisterID base)
{
m_formatter.oneByteOp8(OP_GROUP1_EbIb, GROUP1_OP_ADD, base, offset);
m_formatter.immediate8(imm);
}
void addb_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp8(OP_GROUP1_EbIb, GROUP1_OP_ADD, base, index, scale, offset);
m_formatter.immediate8(imm);
}
void addw_im(int imm, int offset, RegisterID base)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp8(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp8(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);
m_formatter.immediate16(imm);
}
}
void addw_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp8(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, index, scale, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp8(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, index, scale, offset);
m_formatter.immediate16(imm);
}
}
void addq_rr(RegisterID src, RegisterID dst)
{
m_formatter.oneByteOp64(OP_ADD_EvGv, src, dst);
}
void addq_mr(int offset, RegisterID base, RegisterID dst)
{
m_formatter.oneByteOp64(OP_ADD_GvEv, dst, base, offset);
}
void addq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
{
m_formatter.oneByteOp64(OP_ADD_GvEv, dst, base, index, scale, offset);
}
void addq_rm(RegisterID src, int offset, RegisterID base)
{
m_formatter.oneByteOp64(OP_ADD_EvGv, src, base, offset);
}
void addq_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp64(OP_ADD_EvGv, src, base, index, scale, offset);
}
void addq_ir(int imm, RegisterID dst)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst);
m_formatter.immediate8(imm);
} else {
if (dst == X86Registers::eax)
m_formatter.oneByteOp64(OP_ADD_EAXIv);
else
m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);
m_formatter.immediate32(imm);
}
}
void addq_im(int imm, int offset, RegisterID base)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);
m_formatter.immediate32(imm);
}
}
void addq_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, index, scale, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, index, scale, offset);
m_formatter.immediate32(imm);
}
}
void andl_rr(RegisterID src, RegisterID dst)
{
m_formatter.oneByteOp(OP_AND_EvGv, src, dst);
}
void andl_mr(int offset, RegisterID base, RegisterID dst)
{
m_formatter.oneByteOp(OP_AND_GvEv, dst, base, offset);
}
void andl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
{
m_formatter.oneByteOp(OP_AND_GvEv, dst, base, index, scale, offset);
}
void andw_mr(int offset, RegisterID base, RegisterID dst)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
andl_mr(offset, base, dst);
}
void andw_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
andl_mr(offset, base, index, scale, dst);
}
void andl_rm(RegisterID src, int offset, RegisterID base)
{
m_formatter.oneByteOp(OP_AND_EvGv, src, base, offset);
}
void andl_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp(OP_AND_EvGv, src, base, index, scale, offset);
}
void andw_rm(RegisterID src, int offset, RegisterID base)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
andl_rm(src, offset, base);
}
void andw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
andl_rm(src, offset, base, index, scale);
}
void andb_rm(RegisterID src, int offset, RegisterID base)
{
m_formatter.oneByteOp(OP_AND_EvGb, src, base, offset);
}
void andb_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp(OP_AND_EvGb, src, base, index, scale, offset);
}
void andl_ir(int imm, RegisterID dst)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, dst);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, dst);
m_formatter.immediate32(imm);
}
}
void andl_im(int imm, int offset, RegisterID base)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, base, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, base, offset);
m_formatter.immediate32(imm);
}
}
void andl_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, base, index, scale, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, base, index, scale, offset);
m_formatter.immediate32(imm);
}
}
void andw_im(int imm, int offset, RegisterID base)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, base, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, base, offset);
m_formatter.immediate16(imm);
}
}
void andw_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.prefix(PRE_OPERAND_SIZE);
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, base, index, scale, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, base, index, scale, offset);
m_formatter.immediate16(imm);
}
}
void andb_im(int imm, int offset, RegisterID base)
{
m_formatter.oneByteOp(OP_GROUP1_EbIb, GROUP1_OP_AND, base, offset);
m_formatter.immediate8(imm);
}
void andb_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp(OP_GROUP1_EbIb, GROUP1_OP_AND, base, index, scale, offset);
m_formatter.immediate8(imm);
}
void andq_rr(RegisterID src, RegisterID dst)
{
m_formatter.oneByteOp64(OP_AND_EvGv, src, dst);
}
void andq_ir(int imm, RegisterID dst)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_AND, dst);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_AND, dst);
m_formatter.immediate32(imm);
}
}
void andq_mr(int offset, RegisterID base, RegisterID dst)
{
m_formatter.oneByteOp64(OP_AND_GvEv, dst, base, offset);
}
void andq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
{
m_formatter.oneByteOp64(OP_AND_GvEv, dst, base, index, scale, offset);
}
void andq_rm(RegisterID src, int offset, RegisterID base)
{
m_formatter.oneByteOp64(OP_AND_EvGv, src, base, offset);
}
void andq_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp64(OP_AND_EvGv, src, base, index, scale, offset);
}
void andq_im(int imm, int offset, RegisterID base)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_AND, base, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_AND, base, offset);
m_formatter.immediate32(imm);
}
}
void andq_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
{
if (CAN_SIGN_EXTEND_8_32(imm)) {
m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_AND, base, index, scale, offset);
m_formatter.immediate8(imm);
} else {
m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_AND, base, index, scale, offset);
m_formatter.immediate32(imm);
}
}
void dec_r(RegisterID dst)
{
m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP1_OP_OR, dst);
}
void decq_r(RegisterID dst)
{
m_formatter.oneByteOp64(OP_GROUP5_Ev, GROUP1_OP_OR, dst);
}
// Only used for testing purposes.
void illegalInstruction()
{
m_formatter.twoByteOp(OP2_UD2);
}
void inc_r(RegisterID dst)
{
m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP1_OP_ADD, dst);
}
void incq_r(RegisterID dst)
{
m_formatter.oneByteOp64(OP_GROUP5_Ev, GROUP1_OP_ADD, dst);
}
void incq_m(int offset, RegisterID base)
{
m_formatter.oneByteOp64(OP_GROUP5_Ev, GROUP1_OP_ADD, base, offset);
}
void incq_m(int offset, RegisterID base, RegisterID index, int scale)
{
m_formatter.oneByteOp64(OP_GROUP5_Ev, GROUP1_OP_ADD, base, index, scale, offset);
}
void negl_r(RegisterID dst)
{
m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NEG, dst);
}
void negq_r(RegisterID dst)
{
m_formatter.oneByteOp64(OP_GROUP3_Ev, GROUP3_OP_NEG, dst);
}