static constexpr size_t nearJumpRange = 16 * MB;

static constexpr RegisterID dataTempRegister = ARMRegisters::ip;

static constexpr RegisterID addressTempRegister = ARMRegisters::r6;

// d15 is host/C ABI callee save, but is volatile in the VM/JS ABI. We use

// this as scratch register so we can use the full range of d0-d7 as

// temporary, and in particular as Wasm argument/return register.

static constexpr ARMRegisters::FPDoubleRegisterID fpTempRegister = ARMRegisters::d15;

inline ARMRegisters::FPSingleRegisterID fpTempRegisterAsSingle() { return ARMRegisters::asSingle(fpTempRegister); }

// In the Thumb-2 instruction set, instructions operating only on registers r0-r7 can often

// be encoded using 16-bit encodings, while the use of registers r8 and above often require

// 32-bit encodings, so prefer to use the addressTemporary (r6) whenever possible.

inline RegisterID bestTempRegister(RegisterID excluded)

{

if (excluded == addressTempRegister)

return dataTempRegister;

return addressTempRegister;

}

template<typename MacroAssemblerType, typename Condition, typename ...Args>

friend void JSC::MacroAssemblerHelpers::load8OnCondition(MacroAssemblerType&, Condition, Args...);

template<typename MacroAssemblerType, typename Condition, typename ...Args>

friend void JSC::MacroAssemblerHelpers::load16OnCondition(MacroAssemblerType&, Condition, Args...);

struct BoundsNonDoubleWordOffset {

static bool within(intptr_t value)

{

return (value >= -0xff) && (value <= 0xfff);

}

};

struct BoundsDoubleWordOffset {

static bool within(intptr_t value)

{

if (value < 0)

value = -value;

return !(value & ~0x3fc);

}

};

#define DUMMY_REGISTER_VALUE(id, name, r, cs) 0,

static constexpr unsigned numGPRs = std::initializer_list<int>({ FOR_EACH_GP_REGISTER(DUMMY_REGISTER_VALUE) }).size();

static constexpr unsigned numFPRs = std::initializer_list<int>({ FOR_EACH_FP_REGISTER(DUMMY_REGISTER_VALUE) }).size();

#undef DUMMY_REGISTER_VALUE

static constexpr RegisterID s_scratchRegister = addressTempRegister;

RegisterID scratchRegister()

{

RELEASE_ASSERT(m_allowScratchRegister);

return s_scratchRegister;

}

MacroAssemblerARMv7()

: m_makeJumpPatchable(false)

, m_cachedDataTempRegister(this, dataTempRegister)

, m_cachedAddressTempRegister(this, addressTempRegister)

{

}

typedef ARMv7Assembler::LinkRecord LinkRecord;

typedef ARMv7Assembler::JumpType JumpType;

typedef ARMv7Assembler::JumpLinkType JumpLinkType;

typedef ARMv7Assembler::Condition Condition;

static constexpr ARMv7Assembler::Condition DefaultCondition = ARMv7Assembler::ConditionInvalid;

static constexpr ARMv7Assembler::JumpType DefaultJump = ARMv7Assembler::JumpNoConditionFixedSize;

static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)

{

return value >= -255 && value <= 255;

}

Vector<LinkRecord, 0, UnsafeVectorOverflow>& jumpsToLink() LIFETIME_BOUND { return m_assembler.jumpsToLink(); }

static bool canCompact(JumpType jumpType) { return ARMv7Assembler::canCompact(jumpType); }

static JumpLinkType computeJumpType(LinkRecord& record, const uint8_t* from, const uint8_t* to) { return ARMv7Assembler::computeJumpType(record, from, to); }

static int jumpSizeDelta(JumpType jumpType, JumpLinkType jumpLinkType) { return ARMv7Assembler::jumpSizeDelta(jumpType, jumpLinkType); }

template<RepatchingInfo repatch>

ALWAYS_INLINE static void link(LinkRecord& record, uint8_t* from, const uint8_t* fromInstruction, uint8_t* to) { return ARMv7Assembler::link<repatch>(record, from, fromInstruction, to); }

struct ArmAddress {

enum AddressType {

HasOffset,

HasIndex,

} type;

RegisterID base;

union {

int32_t offset;

struct {

RegisterID index;

Scale scale;

};

} u;

explicit ArmAddress(RegisterID base, int32_t offset = 0)

: type(HasOffset)

, base(base)

{

u.offset = offset;

}

explicit ArmAddress(RegisterID base, RegisterID index, Scale scale = TimesOne)

: type(HasIndex)

, base(base)

{

u.index = index;

u.scale = scale;

}

};

enum RelationalCondition {

Equal = ARMv7Assembler::ConditionEQ,

NotEqual = ARMv7Assembler::ConditionNE,

Above = ARMv7Assembler::ConditionHI,

AboveOrEqual = ARMv7Assembler::ConditionHS,

Below = ARMv7Assembler::ConditionLO,

BelowOrEqual = ARMv7Assembler::ConditionLS,

GreaterThan = ARMv7Assembler::ConditionGT,

GreaterThanOrEqual = ARMv7Assembler::ConditionGE,

LessThan = ARMv7Assembler::ConditionLT,

LessThanOrEqual = ARMv7Assembler::ConditionLE

};

static constexpr ARMv7Assembler::Condition armV7ConditionForHigh32(RelationalCondition cond)

{

switch (cond) {

case GreaterThan:

case GreaterThanOrEqual:

return ARMv7Assembler::ConditionGT;

case LessThan:

case LessThanOrEqual:

return ARMv7Assembler::ConditionLT;

case Above:

case AboveOrEqual:

return ARMv7Assembler::ConditionHI;

case Below:

case BelowOrEqual:

return ARMv7Assembler::ConditionLO;

case NotEqual:

return ARMv7Assembler::ConditionNE;

case Equal:

// Equal can never be determined from high alone (needs both parts to match)

return ARMv7Assembler::ConditionInvalid;

default:

RELEASE_ASSERT_NOT_REACHED();

return ARMv7Assembler::ConditionInvalid;

}

}

static constexpr ARMv7Assembler::Condition armV7ConditionForLow32(RelationalCondition cond)

{

switch (cond) {

case GreaterThan:

case Above:

return ARMv7Assembler::ConditionHI;

case GreaterThanOrEqual:

case AboveOrEqual:

return ARMv7Assembler::ConditionHS;

case LessThan:

case Below:

return ARMv7Assembler::ConditionLO;

case LessThanOrEqual:

case BelowOrEqual:

return ARMv7Assembler::ConditionLS;

case NotEqual:

return ARMv7Assembler::ConditionNE;

case Equal:

return ARMv7Assembler::ConditionEQ;

default:

RELEASE_ASSERT_NOT_REACHED();

return ARMv7Assembler::ConditionInvalid;

}

}

enum ResultCondition {

Carry = ARMv7Assembler::ConditionCS,

Overflow = ARMv7Assembler::ConditionVS,

Signed = ARMv7Assembler::ConditionMI,

PositiveOrZero = ARMv7Assembler::ConditionPL,

Zero = ARMv7Assembler::ConditionEQ,

NonZero = ARMv7Assembler::ConditionNE

};

enum DoubleCondition {

// These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.

DoubleEqualAndOrdered = ARMv7Assembler::ConditionEQ,

DoubleNotEqualAndOrdered = ARMv7Assembler::ConditionVC, // Not the right flag! check for this & handle differently.

DoubleGreaterThanAndOrdered = ARMv7Assembler::ConditionGT,

DoubleGreaterThanOrEqualAndOrdered = ARMv7Assembler::ConditionGE,

DoubleLessThanAndOrdered = ARMv7Assembler::ConditionLO,

DoubleLessThanOrEqualAndOrdered = ARMv7Assembler::ConditionLS,

// If either operand is NaN, these conditions always evaluate to true.

DoubleEqualOrUnordered = ARMv7Assembler::ConditionVS, // Not the right flag! check for this & handle differently.

DoubleNotEqualOrUnordered = ARMv7Assembler::ConditionNE,

DoubleGreaterThanOrUnordered = ARMv7Assembler::ConditionHI,

DoubleGreaterThanOrEqualOrUnordered = ARMv7Assembler::ConditionHS,

DoubleLessThanOrUnordered = ARMv7Assembler::ConditionLT,

DoubleLessThanOrEqualOrUnordered = ARMv7Assembler::ConditionLE,

};

static constexpr RegisterID stackPointerRegister = ARMRegisters::sp;

static constexpr RegisterID framePointerRegister = ARMRegisters::fp;

static constexpr RegisterID linkRegister = ARMRegisters::lr;

// Integer arithmetic operations:

//

// Operations are typically two operand - operation(source, srcDst)

// For many operations the source may be an TrustedImm32, the srcDst operand

// may often be a memory location (explicitly described using an Address

// object).

void add32(RegisterID src, RegisterID dest)

{

m_assembler.add(dest, dest, src);

}

void add32(RegisterID left, RegisterID right, RegisterID dest)

{

m_assembler.add(dest, left, right);

}

void add32(TrustedImm32 imm, RegisterID dest)

{

add32(imm, dest, dest);

}

void add32(AbsoluteAddress src, RegisterID dest)

{

load32(setupArmAddress(src), dataTempRegister);

add32(dataTempRegister, dest);

}

void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

// Avoid unpredictable instruction if the destination is the stack pointer

if (dest == ARMRegisters::sp && src != dest) {

RegisterID scratch = getCachedAddressTempRegisterIDAndInvalidate();

add32(imm, src, scratch);

move(scratch, dest);

return;

}

ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

if (armImm.isValid()) {

m_assembler.add(dest, src, armImm);

return;

}

armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(-imm.m_value);

if (armImm.isValid()) {

m_assembler.sub(dest, src, armImm);

return;

}

move(imm, dataTempRegister);

m_assembler.add(dest, src, dataTempRegister);

}

void add32(TrustedImm32 imm, Address address)

{

constexpr bool updateFlags = false;

add32Impl(imm, address, updateFlags);

}

void add32(Address src, RegisterID dest)

{

// load32 will invalidate the cachedDataTempRegister() for us

load32(src, dataTempRegister);

add32(dataTempRegister, dest);

}

void add32(TrustedImm32 imm, AbsoluteAddress address)

{

constexpr bool updateFlags = false;

add32Impl(imm, address, updateFlags);

}

void add8(TrustedImm32 imm, Address address)

{

load8(address, dataTempRegister);

add32(imm, dataTempRegister, dataTempRegister);

store8(dataTempRegister, address);

}

void getEffectiveAddress(BaseIndex address, RegisterID dest)

{

RegisterID scratch = getCachedAddressTempRegisterIDAndInvalidate();

m_assembler.lsl(scratch, address.index, static_cast<int>(address.scale));

m_assembler.add(dest, address.base, scratch);

if (address.offset)

add32(TrustedImm32(address.offset), dest);

}

void addPtrNoFlags(TrustedImm32 imm, RegisterID srcDest)

{

add32(imm, srcDest);

}

void add64(TrustedImm32 imm, AbsoluteAddress address)

{

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

load32(setupArmAddress(address), scratch);

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

if (armImm.isValid())

m_assembler.add_S(scratch, scratch, armImm);

else {

move(imm, addressTempRegister);

m_assembler.add_S(scratch, scratch, addressTempRegister);

move(TrustedImmPtr(address.m_ptr), addressTempRegister);

}

m_assembler.str(scratch, addressTempRegister, ARMThumbImmediate::makeUInt12(0));

m_assembler.ldr(scratch, addressTempRegister, ARMThumbImmediate::makeUInt12(4));

m_assembler.adc(scratch, scratch, ARMThumbImmediate::makeEncodedImm(imm.m_value >> 31));

m_assembler.str(scratch, addressTempRegister, ARMThumbImmediate::makeUInt12(4));

}

void add64(RegisterID op1Hi, RegisterID op1Lo, RegisterID op2Hi, RegisterID op2Lo, RegisterID destHi, RegisterID destLo)

{

if (destLo != op1Hi && destLo != op2Hi) {

m_assembler.add_S(destLo, op1Lo, op2Lo);

m_assembler.adc(destHi, op1Hi, op2Hi);

} else {

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.add_S(scratch, op1Lo, op2Lo);

m_assembler.adc(destHi, op1Hi, op2Hi);

move(scratch, destLo);

}

}

void and64(RegisterID op1Hi, RegisterID op1Lo, RegisterID op2Hi, RegisterID op2Lo, RegisterID destHi, RegisterID destLo)

{

if (destHi != op1Lo && destHi != op2Lo) {

m_assembler.ARM_and(destHi, op1Hi, op2Hi);

m_assembler.ARM_and(destLo, op1Lo, op2Lo);

} else {

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.ARM_and(scratch, op1Hi, op2Hi);

m_assembler.ARM_and(destLo, op1Lo, op2Lo);

move(scratch, destHi);

}

}

void mul64(RegisterID op1Hi, RegisterID op1Lo, RegisterID op2Hi, RegisterID op2Lo, RegisterID destHi, RegisterID destLo)

{

// Check if dest registers will clobber the high parts we need later

if (destLo != op1Hi && destLo != op2Hi && destHi != op1Hi && destHi != op2Hi) {

// No overlap - direct computation

m_assembler.umull(destLo, destHi, op1Lo, op2Lo);

m_assembler.mla(destHi, op1Hi, op2Lo, destHi);

m_assembler.mla(destHi, op1Lo, op2Hi, destHi);

} else {

// Overlap exists - compute middle terms first into scratch, then add

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.mul(scratch, op1Hi, op2Lo);

m_assembler.mla(scratch, op1Lo, op2Hi, scratch);

m_assembler.umull(destLo, destHi, op1Lo, op2Lo);

add32(scratch, destHi);

}

}

void and16(Address src, RegisterID dest)

{

load16(src, dataTempRegister);

and32(dataTempRegister, dest);

}

void and32(RegisterID op1, RegisterID op2, RegisterID dest)

{

m_assembler.ARM_and(dest, op1, op2);

}

void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

if (imm.m_value == -1)

return move(src, dest);

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

if (armImm.isValid()) {

m_assembler.ARM_and(dest, src, armImm);

return;

}

armImm = ARMThumbImmediate::makeEncodedImm(~imm.m_value);

if (armImm.isValid()) {

m_assembler.bic(dest, src, armImm);

return;

}

move(imm, dataTempRegister);

m_assembler.ARM_and(dest, src, dataTempRegister);

}

void and32(RegisterID src, RegisterID dest)

{

and32(dest, src, dest);

}

void and32(TrustedImm32 imm, RegisterID dest)

{

and32(imm, dest, dest);

}

void and32(Address src, RegisterID dest)

{

load32(src, dataTempRegister);

and32(dataTempRegister, dest);

}

void countLeadingZeros32(RegisterID src, RegisterID dest)

{

m_assembler.clz(dest, src);

}

void countTrailingZeros32(RegisterID src, RegisterID dest)

{

m_assembler.rbit(dest, src);

m_assembler.clz(dest, dest);

}

void countLeadingZeros64(RegisterID srcHi, RegisterID srcLo, RegisterID destHi, RegisterID destLo)

{

if (destLo != srcLo) {

m_assembler.clz(destLo, srcHi);

m_assembler.cmp(destLo, ARMThumbImmediate::makeEncodedImm(32));

Jump done = makeBranch(ARMv7Assembler::ConditionNE);

m_assembler.clz(destLo, srcLo);

m_assembler.add(destLo, destLo, ARMThumbImmediate::makeEncodedImm(32));

done.link(this);

xor32(destHi, destHi);

} else {

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

move(srcLo, scratch);

m_assembler.clz(destLo, srcHi);

m_assembler.cmp(destLo, ARMThumbImmediate::makeEncodedImm(32));

Jump done = makeBranch(ARMv7Assembler::ConditionNE);

m_assembler.clz(destLo, scratch);

m_assembler.add(destLo, destLo, ARMThumbImmediate::makeEncodedImm(32));

done.link(this);

xor32(destHi, destHi);

}

}

void countTrailingZeros64(RegisterID srcHi, RegisterID srcLo, RegisterID destHi, RegisterID destLo)

{

if (destLo != srcHi) {

countTrailingZeros32(srcLo, destLo);

m_assembler.cmp(destLo, ARMThumbImmediate::makeEncodedImm(32));

Jump done = makeBranch(ARMv7Assembler::ConditionNE);

countTrailingZeros32(srcHi, destLo);

m_assembler.add(destLo, destLo, ARMThumbImmediate::makeEncodedImm(32));

done.link(this);

xor32(destHi, destHi);

} else {

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

move(srcHi, scratch);

countTrailingZeros32(srcLo, destLo);

m_assembler.cmp(destLo, ARMThumbImmediate::makeEncodedImm(32));

Jump done = makeBranch(ARMv7Assembler::ConditionNE);

countTrailingZeros32(scratch, destLo);

m_assembler.add(destLo, destLo, ARMThumbImmediate::makeEncodedImm(32));

done.link(this);

xor32(destHi, destHi);

}

}

void compare64(RelationalCondition cond, RegisterID lhsHi, RegisterID lhsLo, RegisterID rhsHi, RegisterID rhsLo, RegisterID dest)

{

if (cond == RelationalCondition::Equal || cond == RelationalCondition::NotEqual) {

// For Equal/NotEqual, we can optimize to only set one value conditionally

// NotEqual: default to 1, change to 0 only if both parts equal

// Equal: default to 0, change to 1 only if both parts equal

if (dest != lhsHi && dest != rhsHi && dest != lhsLo && dest != rhsLo) {

m_assembler.mov(dest, ARMThumbImmediate::makeEncodedImm(cond == RelationalCondition::NotEqual ? 1 : 0));

m_assembler.cmp(lhsHi, rhsHi);

Jump done = makeBranch(ARMv7Assembler::ConditionNE);

m_assembler.cmp(lhsLo, rhsLo);

// Only need to set the "opposite" value when both parts match

m_assembler.it(ARMv7Assembler::ConditionEQ);

m_assembler.mov(dest, ARMThumbImmediate::makeEncodedImm(cond == RelationalCondition::NotEqual ? 0 : 1));

done.link(this);

} else {

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.mov(scratch, ARMThumbImmediate::makeEncodedImm(cond == RelationalCondition::NotEqual ? 1 : 0));

m_assembler.cmp(lhsHi, rhsHi);

Jump done = makeBranch(ARMv7Assembler::ConditionNE);

m_assembler.cmp(lhsLo, rhsLo);

m_assembler.it(ARMv7Assembler::ConditionEQ);

m_assembler.mov(scratch, ARMThumbImmediate::makeEncodedImm(cond == RelationalCondition::NotEqual ? 0 : 1));

done.link(this);

move(scratch, dest);

}

return;

}

ARMv7Assembler::Condition hiCondition = armV7ConditionForHigh32(cond);

ARMv7Assembler::Condition loCondition = armV7ConditionForLow32(cond);

if (dest != lhsLo && dest != rhsLo && dest != lhsHi && dest != rhsHi) {

// No aliasing - use ITE blocks with 1 branch

m_assembler.cmp(lhsHi, rhsHi);

m_assembler.it(hiCondition, false);

m_assembler.mov(dest, ARMThumbImmediate::makeEncodedImm(1));

m_assembler.mov(dest, ARMThumbImmediate::makeEncodedImm(0));

Jump done = makeBranch(ARMv7Assembler::ConditionNE);

m_assembler.cmp(lhsLo, rhsLo);

m_assembler.it(loCondition, false);

m_assembler.mov(dest, ARMThumbImmediate::makeEncodedImm(1));

m_assembler.mov(dest, ARMThumbImmediate::makeEncodedImm(0));

done.link(this);

} else {

// dest aliases with source - use scratch

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.cmp(lhsHi, rhsHi);

m_assembler.it(hiCondition, false);

m_assembler.mov(scratch, ARMThumbImmediate::makeEncodedImm(1));

m_assembler.mov(scratch, ARMThumbImmediate::makeEncodedImm(0));

Jump done = makeBranch(ARMv7Assembler::ConditionNE);

m_assembler.cmp(lhsLo, rhsLo);

m_assembler.it(loCondition, false);

m_assembler.mov(scratch, ARMThumbImmediate::makeEncodedImm(1));

m_assembler.mov(scratch, ARMThumbImmediate::makeEncodedImm(0));

done.link(this);

move(scratch, dest);

}

}

void lshiftUnchecked(RegisterID src, RegisterID shiftAmount, RegisterID dest)

{

m_assembler.lsl(dest, src, shiftAmount);

}

void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)

{

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

// Clamp the shift to the range 0..31

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f);

ASSERT(armImm.isValid());

m_assembler.ARM_and(scratch, shiftAmount, armImm);

m_assembler.lsl(dest, src, scratch);

}

void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)

{

if (!(imm.m_value & 0x1f))

move(src, dest);

else

m_assembler.lsl(dest, src, imm.m_value & 0x1f);

}

void lshift32(TrustedImm32 imm, RegisterID shiftAmount, RegisterID dest)

{

// Clamp the shift to the range 0..31

m_assembler.ARM_and(dest, shiftAmount, ARMThumbImmediate::makeEncodedImm(0x1f));

move(imm, getCachedDataTempRegisterIDAndInvalidate());

m_assembler.lsl(dest, dataTempRegister, dest);

}

void lshift32(RegisterID shiftAmount, RegisterID dest)

{

lshift32(dest, shiftAmount, dest);

}

void lshift32(TrustedImm32 imm, RegisterID dest)

{

lshift32(dest, imm, dest);

}

void mul32(RegisterID src, RegisterID dest)

{

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.smull(dest, scratch, dest, src);

}

void mul32(RegisterID left, RegisterID right, RegisterID dest)

{

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.smull(dest, scratch, left, right);

}

void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

move(imm, dataTempRegister);

cachedDataTempRegister().invalidate();

m_assembler.smull(dest, dataTempRegister, src, dataTempRegister);

}

void uMull32(RegisterID left, RegisterID right, RegisterID destHi, RegisterID destLo)

{

m_assembler.umull(destLo, destHi, left, right);

}

#if HAVE(ARM_IDIV_INSTRUCTIONS)

// FIXME: Add more of div flavors.

void div32(RegisterID left, RegisterID right, RegisterID dest)

{

m_assembler.sdiv(dest, left, right);

}

#endif

void neg32(RegisterID srcDest)

{

m_assembler.neg(srcDest, srcDest);

}

void neg32(RegisterID src, RegisterID dest)

{

m_assembler.neg(dest, src);

}

void or8(TrustedImm32 imm, AbsoluteAddress address)

{

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

load8(setupArmAddress(address), dataTempRegister);

if (armImm.isValid()) {

m_assembler.orr(dataTempRegister, dataTempRegister, armImm);

store8(dataTempRegister, Address(addressTempRegister));

} else {

move(imm, addressTempRegister);

m_assembler.orr(dataTempRegister, dataTempRegister, addressTempRegister);

move(TrustedImmPtr(address.m_ptr), addressTempRegister);

store8(dataTempRegister, Address(addressTempRegister));

}

}

void or16(TrustedImm32 imm, AbsoluteAddress dest)

{

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

load16(setupArmAddress(dest), dataTempRegister);

if (armImm.isValid()) {

m_assembler.orr(dataTempRegister, dataTempRegister, armImm);

store16(dataTempRegister, Address(addressTempRegister));

} else {

move(imm, addressTempRegister);

m_assembler.orr(dataTempRegister, dataTempRegister, addressTempRegister);

move(TrustedImmPtr(dest.m_ptr), addressTempRegister);

store16(dataTempRegister, Address(addressTempRegister));

}

}

void or16(RegisterID mask, AbsoluteAddress dest)

{

load16(setupArmAddress(dest), dataTempRegister);

m_assembler.orr(dataTempRegister, dataTempRegister, mask);

store16(dataTempRegister, Address(addressTempRegister));

}

void or32(RegisterID src, RegisterID dest)

{

m_assembler.orr(dest, dest, src);

}

void or32(RegisterID src, AbsoluteAddress dest)

{

load32(setupArmAddress(dest), dataTempRegister);

or32(src, dataTempRegister);

store32(dataTempRegister, Address(addressTempRegister));

}

void or32(RegisterID src, Address dest)

{

load32(dest, dataTempRegister);

or32(src, dataTempRegister);

store32(dataTempRegister, dest);

}

void or32(TrustedImm32 imm, AbsoluteAddress address)

{

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

load32(setupArmAddress(address), dataTempRegister);

if (armImm.isValid()) {

m_assembler.orr(dataTempRegister, dataTempRegister, armImm);

store32(dataTempRegister, Address(addressTempRegister));

} else {

move(imm, addressTempRegister);

m_assembler.orr(dataTempRegister, dataTempRegister, addressTempRegister);

move(TrustedImmPtr(address.m_ptr), addressTempRegister);

store32(dataTempRegister, Address(addressTempRegister));

}

}

void or32(TrustedImm32 imm, Address address)

{

load32(address, dataTempRegister);

or32(imm, dataTempRegister, dataTempRegister);

store32(dataTempRegister, address);

}

void or32(TrustedImm32 imm, RegisterID dest)

{

or32(imm, dest, dest);

}

void or32(RegisterID op1, RegisterID op2, RegisterID dest)

{

m_assembler.orr(dest, op1, op2);

}

void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

if (armImm.isValid())

m_assembler.orr(dest, src, armImm);

else {

ASSERT(src != dataTempRegister);

move(imm, dataTempRegister);

m_assembler.orr(dest, src, dataTempRegister);

}

}

void or64(RegisterID op1Hi, RegisterID op1Lo, RegisterID op2Hi, RegisterID op2Lo, RegisterID destHi, RegisterID destLo)

{

if (destLo != op1Hi && destLo != op2Hi) {

m_assembler.orr(destLo, op1Lo, op2Lo);

m_assembler.orr(destHi, op1Hi, op2Hi);

} else {

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.orr(scratch, op1Lo, op2Lo);

m_assembler.orr(destHi, op1Hi, op2Hi);

move(scratch, destLo);

}

}

void rotateRight32(RegisterID op1, RegisterID op2, RegisterID dest)

{

m_assembler.ror(dest, op1, op2);

}

void rotateRight32(RegisterID src, TrustedImm32 imm, RegisterID dest)

{

if (!imm.m_value)

move(src, dest);

else

m_assembler.ror(dest, src, imm.m_value & 0x1f);

}

void rotateRight32(TrustedImm32 imm, RegisterID srcDst)

{

rotateRight32(srcDst, imm, srcDst);

}

void rotateLeft32(RegisterID src, RegisterID shift, RegisterID dest)

{

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.ARM_and(scratch, shift, ARMThumbImmediate::makeEncodedImm(0x1f));

m_assembler.sub(scratch, ARMThumbImmediate::makeUInt12(32), scratch);

m_assembler.ror(dest, src, scratch);

}

void rotateLeft32(RegisterID src, TrustedImm32 shift, RegisterID dest)

{

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

move(shift, scratch);

m_assembler.ARM_and(scratch, scratch, ARMThumbImmediate::makeEncodedImm(0x1f));

m_assembler.sub(scratch, ARMThumbImmediate::makeUInt12(32), scratch);

m_assembler.ror(dest, src, scratch);

}

void rshiftUnchecked(RegisterID src, RegisterID shiftAmount, RegisterID dest)

{

m_assembler.asr(dest, src, shiftAmount);

}

void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)

{

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

// Clamp the shift to the range 0..31

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f);

ASSERT(armImm.isValid());

m_assembler.ARM_and(scratch, shiftAmount, armImm);

m_assembler.asr(dest, src, scratch);

}

void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)

{

if (!(imm.m_value & 0x1f))

move(src, dest);

else

m_assembler.asr(dest, src, imm.m_value & 0x1f);

}

void rshift32(RegisterID shiftAmount, RegisterID dest)

{

rshift32(dest, shiftAmount, dest);

}

void rshift32(TrustedImm32 imm, RegisterID dest)

{

rshift32(dest, imm, dest);

}

void rshift32(TrustedImm32 imm, RegisterID shiftAmount, RegisterID dest)

{

// Clamp the shift to the range 0..31

m_assembler.ARM_and(dest, shiftAmount, ARMThumbImmediate::makeEncodedImm(0x1f));

move(imm, getCachedDataTempRegisterIDAndInvalidate());

m_assembler.asr(dest, dataTempRegister, dest);

}

void urshiftUnchecked(RegisterID src, RegisterID shiftAmount, RegisterID dest)

{

m_assembler.lsr(dest, src, shiftAmount);

}

void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)

{

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

// Clamp the shift to the range 0..31

ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f);

ASSERT(armImm.isValid());

m_assembler.ARM_and(scratch, shiftAmount, armImm);

m_assembler.lsr(dest, src, scratch);

}

void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)

{

if (!(imm.m_value & 0x1f))

move(src, dest);

else

m_assembler.lsr(dest, src, imm.m_value & 0x1f);

}

void urshift32(RegisterID shiftAmount, RegisterID dest)

{

urshift32(dest, shiftAmount, dest);

}

void urshift32(TrustedImm32 imm, RegisterID dest)

{

urshift32(dest, imm, dest);

}

void urshift32(TrustedImm32 imm, RegisterID shiftAmount, RegisterID dest)

{

// Clamp the shift to the range 0..31

m_assembler.ARM_and(dest, shiftAmount, ARMThumbImmediate::makeEncodedImm(0x1f));

move(imm, getCachedDataTempRegisterIDAndInvalidate());

m_assembler.lsr(dest, dataTempRegister, dest);

}

void addUnsignedRightShift32(RegisterID src1, RegisterID src2, TrustedImm32 amount, RegisterID dest)

{

// dest = src1 + (src2 >> amount)

urshift32(src2, amount, dataTempRegister);

add32(src1, dataTempRegister, dest);

}

void sub32(RegisterID src, RegisterID dest)

{

m_assembler.sub(dest, dest, src);

}

void sub32(RegisterID left, RegisterID right, RegisterID dest)

{

m_assembler.sub(dest, left, right);

}

void sub32(RegisterID left, TrustedImm32 right, RegisterID dest)

{

ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(right.m_value);

if (armImm.isValid())

m_assembler.sub(dest, left, armImm);

else {

move(right, dataTempRegister);

m_assembler.sub(dest, left, dataTempRegister);

}

}

void sub32(TrustedImm32 imm, RegisterID dest)

{

ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

if (armImm.isValid())

m_assembler.sub(dest, dest, armImm);

else {

move(imm, dataTempRegister);

m_assembler.sub(dest, dest, dataTempRegister);

}

}

void sub32(TrustedImm32 imm, RegisterID src, RegisterID dest)

{

ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

if (armImm.isValid())

m_assembler.sub(dest, armImm, src);

else {

move(imm, dataTempRegister);

m_assembler.sub(dest, dataTempRegister, src);

}

}

void sub32(TrustedImm32 imm, Address address)

{

load32(address, dataTempRegister);

ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

if (armImm.isValid())

m_assembler.sub(dataTempRegister, dataTempRegister, armImm);

else {

// Hrrrm, since dataTempRegister holds the data loaded,

// use addressTempRegister to hold the immediate.

move(imm, addressTempRegister);

m_assembler.sub(dataTempRegister, dataTempRegister, addressTempRegister);

}

store32(dataTempRegister, address);

}

void sub32(Address src, RegisterID dest)

{

load32(src, dataTempRegister);

sub32(dataTempRegister, dest);

}

void sub32(TrustedImm32 imm, AbsoluteAddress address)

{

load32(setupArmAddress(address), dataTempRegister);

ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

if (armImm.isValid())

m_assembler.sub(dataTempRegister, dataTempRegister, armImm);

else {

// Hrrrm, since dataTempRegister holds the data loaded,

// use addressTempRegister to hold the immediate.

move(imm, addressTempRegister);

m_assembler.sub(dataTempRegister, dataTempRegister, addressTempRegister);

}

store32(dataTempRegister, address.m_ptr);

}

void sub64(RegisterID leftHi, RegisterID leftLo, RegisterID rightHi, RegisterID rightLo, RegisterID destHi, RegisterID destLo)

{

if (destLo != leftHi && destLo != rightHi) {

m_assembler.sub_S(destLo, leftLo, rightLo);

m_assembler.sbc(destHi, leftHi, rightHi);

} else {

RegisterID scratch = getCachedDataTempRegisterIDAndInvalidate();

m_assembler.sub_S(scratch, leftLo, rightLo);

m_assembler.sbc(destHi, leftHi, rightHi);

move(scratch, destLo);

}

}