This repository contains examples that demonstrate the usage of the new features that come with VHDL 2008.

These examples are part of my bachelor thesis.

Every example comes with a batch-script that allows automatic verification and synthesis (you have to add the path to your executables for GHDL, Modelsim, Quartus Prime Lite, Quartus Prime Pro in the beginning of those files)

I will not be held responsible for the code I show here. I will try my best to deliver a error-free implementation with explanation and working testbench. If it does not work for you, does not simulate, synthesize or whatever, don’t hold me responsible.

Feel free to take a look at the code, let yourself be inspired, re-use the code and learn from it.