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stmhal/boards/STM32F7DISC Expand file tree Collapse file tree Original file line number Diff line number Diff line change 2020void STM32F7DISC_board_early_init (void );
2121
2222// HSE is 25MHz
23+ // VCOClock = HSE * PLLN / PLLM = 25 MHz * 432 / 25 = 432 MHz
24+ // SYSCLK = VCOClock / PLLP = 432 MHz / 2 = 216 MHz
25+ // USB/SDMMC/RNG Clock = VCOClock / PLLQ = 432 MHz / 9 = 48 MHz
2326#define MICROPY_HW_CLK_PLLM (25)
24- #define MICROPY_HW_CLK_PLLN (336 )
27+ #define MICROPY_HW_CLK_PLLN (432 )
2528#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
26- #define MICROPY_HW_CLK_PLLQ (7 )
29+ #define MICROPY_HW_CLK_PLLQ (9 )
2730
28- #define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_6
31+ // From the reference manual, for 2.7V to 3.6V
32+ // 151-180 MHz => 5 wait states
33+ // 181-210 MHz => 6 wait states
34+ // 211-216 MHz => 7 wait states
35+ #define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_7 // 210-216 MHz needs 7 wait states
2936
3037// UART config
3138#define MICROPY_HW_UART1_TX_PORT (GPIOA)
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