StackRduino
diff --git a/‎stmhal/hal/f4/src/stm32f4xx_hal_rcc.c‎
Lines changed: 6 additions & 1 deletion b/‎stmhal/hal/f4/src/stm32f4xx_hal_rcc.c‎
Lines changed: 6 additions & 1 deletion
@@ -893,7 +893,12 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void)
       if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
       {
         /* HSE used as PLL clock source */
-        pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+        //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+        // dpgeorge: Adjust the way the arithmetic is done so it retains
+        // precision for the case that pllm doesn't evenly divide HSE_VALUE.
+        // Must be sure not to overflow, so divide by 4 first.  HSE_VALUE
+        // should be a multiple of 4 (being a multiple of 100 is enough).
+        pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;
       }
       else
       {
Original file line number	Diff line number	Diff line change
`@@ -893,7 +893,12 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void)`
`893`	`893`	`if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)`
`894`	`894`	`{`
`895`	`895`	`/* HSE used as PLL clock source */`
`896`		`- pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));`
	`896`	`+ //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));`
	`897`	`+ // dpgeorge: Adjust the way the arithmetic is done so it retains`
	`898`	`+ // precision for the case that pllm doesn't evenly divide HSE_VALUE.`
	`899`	`+ // Must be sure not to overflow, so divide by 4 first. HSE_VALUE`
	`900`	`+ // should be a multiple of 4 (being a multiple of 100 is enough).`
	`901`	`+ pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4;`
`897`	`902`	`}`
`898`	`903`	`else`
`899`	`904`	`{`