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Add DTCM and ITCM support to F7 series
1 parent 0ba541d commit b414f82

8 files changed

Lines changed: 50 additions & 13 deletions

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‎ports/stm/boards/STM32F746xG_fs.ld‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,14 +26,20 @@
2626
* THE SOFTWARE.
2727
*/
2828

29+
/* Entry Point */
30+
ENTRY(Reset_Handler)
31+
32+
_ld_default_stack_size = 24K;
33+
2934
/* Specify the memory areas */
3035
MEMORY
3136
{
3237
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */
3338
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 32K /* sector 0 */
3439
FLASH_FS (rx) : ORIGIN = 0x08008000, LENGTH = 96K /* sectors 1,2,3 are 32K */
3540
FLASH_FIRMWARE (rx) : ORIGIN = 0x08020000, LENGTH = 896K /* sector 4 is 128K, sectors 5,6,7 are 256K */
36-
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K
41+
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
42+
RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 256K /* AXI SRAM */
3743
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 16K
3844
}
3945

@@ -44,7 +50,7 @@ _minimum_heap_size = 16K;
4450
/* Define tho top end of the stack. The stack is full descending so begins just
4551
above last byte of RAM. Note that EABI requires the stack to be 8-byte
4652
aligned for a call. */
47-
_estack = ORIGIN(RAM) + LENGTH(RAM);
53+
_estack = ORIGIN(DTCM) + LENGTH(DTCM);
4854

4955
/* RAM extents for the garbage collector */
5056
_ram_start = ORIGIN(RAM);

‎ports/stm/boards/STM32F767_fs.ld‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,21 @@
22
GNU linker script for STM32F767 with filesystem
33
*/
44

5+
/* Entry Point */
6+
ENTRY(Reset_Handler)
7+
8+
_ld_default_stack_size = 24K;
9+
510
/* Specify the memory areas */
611
MEMORY
712
{
813
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* entire flash */
914
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 32K /* sector 0 */
1015
FLASH_FS (rx) : ORIGIN = 0x08008000, LENGTH = 96K /* sectors 1,2,3 are 32K */
1116
FLASH_FIRMWARE (rx) : ORIGIN = 0x08020000, LENGTH = 1920K /* sector 4 is 128K, sectors 5,6,7 are 256K */
12-
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 512K
17+
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
18+
RAM (xrw) : ORIGIN = 0x20020000, LENGTH = 384K /* AXI SRAM */
19+
ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 16K
1320
}
1421

1522
/* produce a link error if there is not this amount of RAM for these sections */
@@ -19,7 +26,7 @@ _minimum_heap_size = 16K;
1926
/* Define tho top end of the stack. The stack is full descending so begins just
2027
above last byte of RAM. Note that EABI requires the stack to be 8-byte
2128
aligned for a call. */
22-
_estack = ORIGIN(RAM) + LENGTH(RAM);
29+
_estack = ORIGIN(DTCM) + LENGTH(DTCM);
2330

2431
/* RAM extents for the garbage collector */
2532
_ram_start = ORIGIN(RAM);

‎ports/stm/boards/nucleo_f746zg/mpconfigboard.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,14 @@
3333
#define FLASH_SIZE (0x100000)
3434
#define FLASH_PAGE_SIZE (0x4000)
3535

36+
// H7 and F7 MPU definitions
37+
#define CPY_FLASH_REGION_SIZE ARM_MPU_REGION_SIZE_1MB
38+
#define CPY_ITCM_REGION_SIZE ARM_MPU_REGION_SIZE_16KB
39+
#define CPY_DTCM_REGION_SIZE ARM_MPU_REGION_SIZE_128KB
40+
#define CPY_SRAM_REGION_SIZE ARM_MPU_REGION_SIZE_256KB
41+
#define CPY_SRAM_SUBMASK 0x00
42+
#define CPY_SRAM_START_ADDR 0x20010000
43+
3644
#define HSE_VALUE ((uint32_t)8000000)
3745
#define LSE_VALUE ((uint32_t)32768)
3846
#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal

‎ports/stm/boards/nucleo_f746zg/mpconfigboard.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,5 +10,5 @@ MCU_SERIES = F7
1010
MCU_VARIANT = STM32F746xx
1111
MCU_PACKAGE = LQFP144
1212

13-
LD_COMMON = boards/common_default.ld
13+
LLD_COMMON = boards/common_tcm.ld
1414
LD_FILE = boards/STM32F746xG_fs.ld

‎ports/stm/boards/nucleo_f767zi/mpconfigboard.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,14 @@
3232
#define FLASH_SIZE (0x200000)
3333
#define FLASH_PAGE_SIZE (0x4000)
3434

35+
// H7 and F7 MPU definitions
36+
#define CPY_FLASH_REGION_SIZE ARM_MPU_REGION_SIZE_2MB
37+
#define CPY_ITCM_REGION_SIZE ARM_MPU_REGION_SIZE_16KB
38+
#define CPY_DTCM_REGION_SIZE ARM_MPU_REGION_SIZE_128KB
39+
#define CPY_SRAM_REGION_SIZE ARM_MPU_REGION_SIZE_512KB
40+
#define CPY_SRAM_SUBMASK 0xFC // Mask 512 to 384
41+
#define CPY_SRAM_START_ADDR 0x20020000
42+
3543
#define HSE_VALUE ((uint32_t)8000000)
3644
#define LSE_VALUE ((uint32_t)32768)
3745
#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal

‎ports/stm/boards/nucleo_f767zi/mpconfigboard.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,5 +10,5 @@ MCU_SERIES = F7
1010
MCU_VARIANT = STM32F767xx
1111
MCU_PACKAGE = LQFP144
1212

13-
LD_COMMON = boards/common_default.ld
13+
LD_COMMON = boards/common_tcm.ld
1414
LD_FILE = boards/STM32F767_fs.ld

‎ports/stm/boards/nucleo_h743zi_2/mpconfigboard.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,14 @@
3131

3232
#define FLASH_PAGE_SIZE (0x4000)
3333

34+
// H7 and F7 MPU definitions
35+
#define CPY_FLASH_REGION_SIZE ARM_MPU_REGION_SIZE_2MB
36+
#define CPY_ITCM_REGION_SIZE ARM_MPU_REGION_SIZE_64KB
37+
#define CPY_DTCM_REGION_SIZE ARM_MPU_REGION_SIZE_128KB
38+
#define CPY_SRAM_REGION_SIZE ARM_MPU_REGION_SIZE_512KB
39+
#define CPY_SRAM_SUBMASK 0x00
40+
#define CPY_SRAM_START_ADDR 0x24000000
41+
3442
#define HSE_VALUE ((uint32_t)8000000)
3543
#define LSE_VALUE ((uint32_t)32768)
3644
#define BOARD_HSE_SOURCE (RCC_HSE_BYPASS) // ST boards use the STLink clock signal

‎ports/stm/supervisor/port.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949
#include STM32_HAL_H
5050

5151
//only enable the Reset Handler overwrite for the H7 for now
52-
#if (CPY_STM32H7)
52+
#if (CPY_STM32H7) || (CPY_STM32F7)
5353

5454
// Device memories must be accessed in order.
5555
#define DEVICE 2
@@ -86,7 +86,7 @@ extern uint32_t _ld_itcm_flash_copy;
8686
extern void main(void);
8787
extern void SystemInit(void);
8888

89-
// This replaces the Reset_Handler in startup_*.S and SystemInit in system_*.c.
89+
// This replaces the Reset_Handler in gcc/startup_*.s, calls SystemInit from system_*.c
9090
__attribute__((used, naked)) void Reset_Handler(void) {
9191
__disable_irq();
9292
__set_MSP((uint32_t) &_ld_stack_top);
@@ -105,20 +105,20 @@ __attribute__((used, naked)) void Reset_Handler(void) {
105105

106106
// Mark all the flash the same until instructed otherwise.
107107
MPU->RBAR = ARM_MPU_RBAR(11, 0x08000000U);
108-
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_2MB);
108+
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_FLASH_REGION_SIZE);
109109

110110
// This the ITCM. Set it to read-only because we've loaded everything already and it's easy to
111111
// accidentally write the wrong value to 0x00000000 (aka NULL).
112112
MPU->RBAR = ARM_MPU_RBAR(12, 0x00000000U);
113-
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_64KB);
113+
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_RO, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_ITCM_REGION_SIZE);
114114

115115
// This the DTCM.
116116
MPU->RBAR = ARM_MPU_RBAR(14, 0x20000000U);
117-
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_128KB);
117+
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, CPY_DTCM_REGION_SIZE);
118118

119119
// This is AXI SRAM (D1).
120-
MPU->RBAR = ARM_MPU_RBAR(15, 0x24000000U);
121-
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, NO_SUBREGIONS, ARM_MPU_REGION_SIZE_512KB);
120+
MPU->RBAR = ARM_MPU_RBAR(15, CPY_SRAM_START_ADDR);
121+
MPU->RASR = ARM_MPU_RASR(EXECUTION, ARM_MPU_AP_FULL, NORMAL, NOT_SHAREABLE, CACHEABLE, BUFFERABLE, CPY_SRAM_SUBMASK, CPY_SRAM_REGION_SIZE);
122122

123123
/* Enable MPU */
124124
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);

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