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Merge pull request adafruit#202 from iabdalkader/master
Remove hardcoded PLL_M value
2 parents d30e019 + 4578ced commit 8517bce

2 files changed

Lines changed: 5 additions & 4 deletions

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stm/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,14 +18,15 @@ FATFSSRC=fatfs
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CC3KSRC=cc3k
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DFU=../tools/dfu.py
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TARGET=PYBOARD
21+
OSC_VALUE=8000000
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AS = arm-none-eabi-as
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CC = arm-none-eabi-gcc
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LD = arm-none-eabi-ld
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OBJCOPY = arm-none-eabi-objcopy
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SIZE = arm-none-eabi-size
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28-
CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion -DSTM32F40_41xxx -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=8000000
29+
CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion -DSTM32F40_41xxx -DUSE_STDPERIPH_DRIVER -DHSE_VALUE=$(OSC_VALUE)
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CFLAGS = -I. -I$(PY_SRC) -I$(FATFSSRC) -I$(CMSIS) -I$(STMSRC) -Wall -ansi -std=gnu99 $(CFLAGS_CORTEX_M4) -D$(TARGET)
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#CFLAGS += -I$(STMOTGSRC) -DUSE_HOST_MODE -DUSE_OTG_MODE
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stm/system_stm32f4xx.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,9 @@
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 2
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*-----------------------------------------------------------------------------
57-
* HSE Frequency(Hz) | 8000000 changed dpgeorge
57+
* HSE Frequency(Hz) | HSE_VALUE
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*-----------------------------------------------------------------------------
59-
* PLL_M | 8 changed dpgeorge
59+
* PLL_M | (HSE_VALUE/1000000)
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*-----------------------------------------------------------------------------
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* PLL_N | 336
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*-----------------------------------------------------------------------------
@@ -251,7 +251,7 @@
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/************************* PLL Parameters *************************************/
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
254-
#define PLL_M 8
254+
#define PLL_M (HSE_VALUE/1000000)
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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#define PLL_Q 7
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