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dhalberttannewt
dhalbert
authored and
tannewt
committed
samd51 peripheral clocks were defined as 12MHz, but were really 120MHz
1 parent 1d6bf8e commit 6f662e9

1 file changed

Lines changed: 16 additions & 16 deletions

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‎ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@
4141
* \brief ADC0's Clock frequency
4242
*/
4343
#ifndef CONF_GCLK_ADC0_FREQUENCY
44-
#define CONF_GCLK_ADC0_FREQUENCY 12000000
44+
#define CONF_GCLK_ADC0_FREQUENCY 120000000
4545
#endif
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4747
// <y> DAC Clock Source
@@ -81,7 +81,7 @@
8181
* \brief DAC's Clock frequency
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*/
8383
#ifndef CONF_GCLK_DAC_FREQUENCY
84-
#define CONF_GCLK_DAC_FREQUENCY 12000000
84+
#define CONF_GCLK_DAC_FREQUENCY 120000000
8585
#endif
8686

8787
// <y> EVSYS Channel 0 Clock Source
@@ -122,7 +122,7 @@
122122
*/
123123

124124
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
125-
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000.0
125+
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000.0
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#endif
127127

128128
// <y> EVSYS Channel 1 Clock Source
@@ -163,7 +163,7 @@
163163
*/
164164

165165
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
166-
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000.0
166+
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000.0
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#endif
168168

169169
// <y> EVSYS Channel 2 Clock Source
@@ -204,7 +204,7 @@
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*/
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206206
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
207-
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000.0
207+
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000.0
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#endif
209209

210210
// <y> EVSYS Channel 3 Clock Source
@@ -245,7 +245,7 @@
245245
*/
246246

247247
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
248-
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000.0
248+
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000.0
249249
#endif
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251251
// <y> EVSYS Channel 4 Clock Source
@@ -286,7 +286,7 @@
286286
*/
287287

288288
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
289-
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000.0
289+
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000.0
290290
#endif
291291

292292
// <y> EVSYS Channel 5 Clock Source
@@ -327,7 +327,7 @@
327327
*/
328328

329329
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
330-
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000.0
330+
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000.0
331331
#endif
332332

333333
// <y> EVSYS Channel 6 Clock Source
@@ -368,7 +368,7 @@
368368
*/
369369

370370
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
371-
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000.0
371+
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000.0
372372
#endif
373373

374374
// <y> EVSYS Channel 7 Clock Source
@@ -409,7 +409,7 @@
409409
*/
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411411
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
412-
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000.0
412+
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000.0
413413
#endif
414414

415415
// <y> EVSYS Channel 8 Clock Source
@@ -450,7 +450,7 @@
450450
*/
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452452
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
453-
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000.0
453+
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000.0
454454
#endif
455455

456456
// <y> EVSYS Channel 9 Clock Source
@@ -491,7 +491,7 @@
491491
*/
492492

493493
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
494-
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000.0
494+
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000.0
495495
#endif
496496

497497
// <y> EVSYS Channel 10 Clock Source
@@ -532,7 +532,7 @@
532532
*/
533533

534534
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
535-
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000.0
535+
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000.0
536536
#endif
537537

538538
// <y> EVSYS Channel 11 Clock Source
@@ -573,15 +573,15 @@
573573
*/
574574

575575
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
576-
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000.0
576+
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000.0
577577
#endif
578578

579579
/**
580580
* \def CONF_CPU_FREQUENCY
581581
* \brief CPU's Clock frequency
582582
*/
583583
#ifndef CONF_CPU_FREQUENCY
584-
#define CONF_CPU_FREQUENCY 12000000
584+
#define CONF_CPU_FREQUENCY 120000000
585585
#endif
586586

587587
// <y> RTC Clock Source
@@ -877,7 +877,7 @@
877877
* \brief TC0's Clock frequency
878878
*/
879879
#ifndef CONF_GCLK_TC0_FREQUENCY
880-
#define CONF_GCLK_TC0_FREQUENCY 12000000
880+
#define CONF_GCLK_TC0_FREQUENCY 120000000
881881
#endif
882882

883883
// <y> USB Clock Source

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