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dpgeorgedpgeorge
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stmhal: Clean up DAC code a little.
1 parent 6a388aa commit 6f5e0fe

1 file changed

Lines changed: 29 additions & 24 deletions

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‎stmhal/dac.c‎

Lines changed: 29 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -96,11 +96,18 @@ STATIC void TIM6_Config(uint freq) {
9696
/******************************************************************************/
9797
// Micro Python bindings
9898

99+
typedef enum {
100+
DAC_STATE_RESET,
101+
DAC_STATE_WRITE_SINGLE,
102+
DAC_STATE_BUILTIN_WAVEFORM,
103+
DAC_STATE_DMA_WAVEFORM,
104+
} pyb_dac_state_t;
105+
99106
typedef struct _pyb_dac_obj_t {
100107
mp_obj_base_t base;
101108
uint32_t dac_channel; // DAC_CHANNEL_1 or DAC_CHANNEL_2
102109
DMA_Stream_TypeDef *dma_stream; // DMA1_Stream5 or DMA1_Stream6
103-
mp_uint_t state;
110+
pyb_dac_state_t state;
104111
} pyb_dac_obj_t;
105112

106113
// create the dac object
@@ -163,7 +170,7 @@ STATIC mp_obj_t pyb_dac_make_new(mp_obj_t type_in, mp_uint_t n_args, mp_uint_t n
163170
HAL_DAC_Stop_DMA(&DAC_Handle, dac->dac_channel);
164171
}
165172

166-
dac->state = 0;
173+
dac->state = DAC_STATE_RESET;
167174

168175
// return object
169176
return dac;
@@ -179,13 +186,13 @@ STATIC mp_obj_t pyb_dac_noise(mp_obj_t self_in, mp_obj_t freq) {
179186
// set TIM6 to trigger the DAC at the given frequency
180187
TIM6_Config(mp_obj_get_int(freq));
181188

182-
if (self->state != 2) {
189+
if (self->state != DAC_STATE_BUILTIN_WAVEFORM) {
183190
// configure DAC to trigger via TIM6
184191
DAC_ChannelConfTypeDef config;
185192
config.DAC_Trigger = DAC_TRIGGER_T6_TRGO;
186193
config.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
187194
HAL_DAC_ConfigChannel(&DAC_Handle, &config, self->dac_channel);
188-
self->state = 2;
195+
self->state = DAC_STATE_BUILTIN_WAVEFORM;
189196
}
190197

191198
// set noise wave generation
@@ -209,13 +216,13 @@ STATIC mp_obj_t pyb_dac_triangle(mp_obj_t self_in, mp_obj_t freq) {
209216
// set TIM6 to trigger the DAC at the given frequency
210217
TIM6_Config(mp_obj_get_int(freq));
211218

212-
if (self->state != 2) {
219+
if (self->state != DAC_STATE_BUILTIN_WAVEFORM) {
213220
// configure DAC to trigger via TIM6
214221
DAC_ChannelConfTypeDef config;
215222
config.DAC_Trigger = DAC_TRIGGER_T6_TRGO;
216223
config.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
217224
HAL_DAC_ConfigChannel(&DAC_Handle, &config, self->dac_channel);
218-
self->state = 2;
225+
self->state = DAC_STATE_BUILTIN_WAVEFORM;
219226
}
220227

221228
// set triangle wave generation
@@ -233,12 +240,12 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_dac_triangle_obj, pyb_dac_triangle);
233240
STATIC mp_obj_t pyb_dac_write(mp_obj_t self_in, mp_obj_t val) {
234241
pyb_dac_obj_t *self = self_in;
235242

236-
if (self->state != 1) {
243+
if (self->state != DAC_STATE_WRITE_SINGLE) {
237244
DAC_ChannelConfTypeDef config;
238245
config.DAC_Trigger = DAC_TRIGGER_NONE;
239246
config.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
240247
HAL_DAC_ConfigChannel(&DAC_Handle, &config, self->dac_channel);
241-
self->state = 1;
248+
self->state = DAC_STATE_WRITE_SINGLE;
242249
}
243250

244251
HAL_DAC_SetValue(&DAC_Handle, self->dac_channel, DAC_ALIGN_8B_R, mp_obj_get_int(val));
@@ -258,26 +265,24 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_dac_write_obj, pyb_dac_write);
258265
/// TIM6 is used to control the frequency of the transfer.
259266
// TODO add callback argument, to call when transfer is finished
260267
// TODO add double buffer argument
261-
STATIC const mp_arg_t pyb_dac_write_timed_args[] = {
262-
{ MP_QSTR_data, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
263-
{ MP_QSTR_freq, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
264-
{ MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DMA_NORMAL} },
265-
};
266-
#define PYB_DAC_WRITE_TIMED_NUM_ARGS MP_ARRAY_SIZE(pyb_dac_write_timed_args)
267-
268-
mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
269-
pyb_dac_obj_t *self = args[0];
268+
mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
269+
static const mp_arg_t allowed_args[] = {
270+
{ MP_QSTR_data, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
271+
{ MP_QSTR_freq, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
272+
{ MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DMA_NORMAL} },
273+
};
270274

271275
// parse args
272-
mp_arg_val_t vals[PYB_DAC_WRITE_TIMED_NUM_ARGS];
273-
mp_arg_parse_all(n_args - 1, args + 1, kw_args, PYB_DAC_WRITE_TIMED_NUM_ARGS, pyb_dac_write_timed_args, vals);
276+
pyb_dac_obj_t *self = pos_args[0];
277+
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
278+
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
274279

275280
// get the data to write
276281
mp_buffer_info_t bufinfo;
277-
mp_get_buffer_raise(vals[0].u_obj, &bufinfo, MP_BUFFER_READ);
282+
mp_get_buffer_raise(args[0].u_obj, &bufinfo, MP_BUFFER_READ);
278283

279284
// set TIM6 to trigger the DAC at the given frequency
280-
TIM6_Config(vals[1].u_int);
285+
TIM6_Config(args[1].u_int);
281286

282287
__DMA1_CLK_ENABLE();
283288

@@ -313,7 +318,7 @@ mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *k
313318
DMA_Handle.Init.MemInc = DMA_MINC_ENABLE;
314319
DMA_Handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
315320
DMA_Handle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
316-
DMA_Handle.Init.Mode = vals[2].u_int;
321+
DMA_Handle.Init.Mode = args[2].u_int;
317322
DMA_Handle.Init.Priority = DMA_PRIORITY_HIGH;
318323
DMA_Handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
319324
DMA_Handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL;
@@ -331,12 +336,12 @@ mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *k
331336
DAC_Handle.State = HAL_DAC_STATE_RESET;
332337
HAL_DAC_Init(&DAC_Handle);
333338

334-
if (self->state != 3) {
339+
if (self->state != DAC_STATE_DMA_WAVEFORM) {
335340
DAC_ChannelConfTypeDef config;
336341
config.DAC_Trigger = DAC_TRIGGER_T6_TRGO;
337342
config.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
338343
HAL_DAC_ConfigChannel(&DAC_Handle, &config, self->dac_channel);
339-
self->state = 3;
344+
self->state = DAC_STATE_DMA_WAVEFORM;
340345
}
341346

342347
HAL_DAC_Start_DMA(&DAC_Handle, self->dac_channel, (uint32_t*)bufinfo.buf, bufinfo.len, DAC_ALIGN_8B_R);

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