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dhalbertdhalbert
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Merge pull request adafruit#1418 from dhalbert/feather52840-rgb-qspi-fixes
Don't check for corrupt heap too early; Fix QSPI timing
2 parents 60a509b + 0dfe2db commit 6d60b81

2 files changed

Lines changed: 15 additions & 15 deletions

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‎ports/nrf/supervisor/qspi_flash.c‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -40,15 +40,13 @@
4040

4141
bool spi_flash_command(uint8_t command) {
4242
nrf_qspi_cinstr_conf_t cinstr_cfg = {
43-
.opcode = 0,
44-
.length = 0,
43+
.opcode = command,
44+
.length = 1,
4545
.io2_level = true,
4646
.io3_level = true,
4747
.wipwait = false,
4848
.wren = false
4949
};
50-
cinstr_cfg.opcode = command;
51-
cinstr_cfg.length = 1;
5250
nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
5351
return true;
5452
}
@@ -62,8 +60,8 @@ bool spi_flash_read_command(uint8_t command, uint8_t* response, uint32_t length)
6260
.wipwait = false,
6361
.wren = false
6462
};
65-
nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, response);
66-
return true;
63+
return nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, response) == NRFX_SUCCESS;
64+
6765
}
6866

6967
bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
@@ -75,8 +73,7 @@ bool spi_flash_write_command(uint8_t command, uint8_t* data, uint32_t length) {
7573
.wipwait = false,
7674
.wren = false // We do this manually.
7775
};
78-
nrfx_qspi_cinstr_xfer(&cinstr_cfg, data, NULL);
79-
return true;
76+
return nrfx_qspi_cinstr_xfer(&cinstr_cfg, data, NULL) == NRFX_SUCCESS;
8077
}
8178

8279
bool spi_flash_sector_command(uint8_t command, uint32_t address) {
@@ -91,8 +88,7 @@ bool spi_flash_write_data(uint32_t address, uint8_t* data, uint32_t length) {
9188
}
9289

9390
bool spi_flash_read_data(uint32_t address, uint8_t* data, uint32_t length) {
94-
nrfx_qspi_read(data, length, address);
95-
return true;
91+
return nrfx_qspi_read(data, length, address) == NRFX_SUCCESS;
9692
}
9793

9894
void spi_flash_init(void) {
@@ -115,7 +111,7 @@ void spi_flash_init(void) {
115111
.dpmconfig = false
116112
},
117113
.phy_if = {
118-
.sck_freq = NRF_QSPI_FREQ_32MDIV16, // Start at a slow 2mhz and speed up once we know what we're talking to.
114+
.sck_freq = NRF_QSPI_FREQ_32MDIV16, // Start at a slow 2MHz and speed up once we know what we're talking to.
119115
.sck_delay = 10, // min time CS must stay high before going low again. in unit of 62.5 ns
120116
.spi_mode = NRF_QSPI_MODE_0,
121117
.dpmen = false
@@ -145,14 +141,18 @@ void spi_flash_init_device(const external_flash_device* device) {
145141
// Switch to single output line if the device doesn't support quad programs.
146142
if (!device->supports_qspi_writes) {
147143
NRF_QSPI->IFCONFIG0 &= ~QSPI_IFCONFIG0_WRITEOC_Msk;
148-
NRF_QSPI->IFCONFIG0 |= QSPI_IFCONFIG0_WRITEOC_PP;
144+
NRF_QSPI->IFCONFIG0 |= QSPI_IFCONFIG0_WRITEOC_PP << QSPI_IFCONFIG0_WRITEOC_Pos;
149145
}
150146

151147
// Speed up as much as we can.
152-
uint8_t sckfreq = 0;
148+
// Start at 16 MHz and go down.
149+
// At 32 MHz GD25Q16C doesn't work reliably on Feather 52840, even though it should work up to 104 MHz.
150+
// sckfreq = 0 is 32 Mhz
151+
// sckfreq = 1 is 16 MHz, etc.
152+
uint8_t sckfreq = 1;
153153
while (32000000 / (sckfreq + 1) > device->max_clock_speed_mhz * 1000000 && sckfreq < 16) {
154154
sckfreq += 1;
155155
}
156156
NRF_QSPI->IFCONFIG1 &= ~QSPI_IFCONFIG1_SCKFREQ_Msk;
157-
NRF_QSPI->IFCONFIG1 |= sckfreq << QSPI_IFCONFIG1_SCKDELAY_Pos;
157+
NRF_QSPI->IFCONFIG1 |= sckfreq << QSPI_IFCONFIG1_SCKFREQ_Pos;
158158
}

‎supervisor/shared/stack.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ void allocate_stack(void) {
5656
}
5757

5858
inline bool stack_ok(void) {
59-
return *stack_alloc->ptr == STACK_CANARY_VALUE;
59+
return stack_alloc == NULL || *stack_alloc->ptr == STACK_CANARY_VALUE;
6060
}
6161

6262
inline void assert_heap_ok(void) {

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