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tannewttannewt
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Merge pull request adafruit#649 from dhalbert/3.0_AnalogOut_fixes
Use safe clock freqs for AnalogOut; use DAC REFRESH on SAMD51.
2 parents 5eb3b20 + 5c24023 commit 6a2379f

6 files changed

Lines changed: 20 additions & 16 deletions

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‎ports/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,13 @@
11
// Circuit Python SAMD21 clock tree:
2-
// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK0
2+
// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK0, GCLK1
33
// GCLK0 (48MHz) -> peripherals
4+
// GLCK1 (48MHz divided by 150 = 320Khz) -> DAC peripheral (DAC requires 350KHz or lower)
45

56
// We'd like to use XOSC32K as a ref for DFLL48M on boards with a 32kHz crystal,
67
// but haven't figured that out yet.
78

89
// Used in hpl/core/hpl_init.c to define which clocks should be initialized first.
9-
#define CIRCUITPY_GCLK_INIT_1ST (1 << 0)
10+
#define CIRCUITPY_GCLK_INIT_1ST (1 << 0 | 1 << 1)
1011

1112

1213
/* Auto-generated config file hpl_gclk_config.h */
@@ -127,7 +128,7 @@
127128
// <i> Indicates whether Output Enable is enabled or not
128129
// <id> gclk_arch_gen_1_oe
129130
#ifndef CONF_GCLK_GEN_1_OE
130-
#define CONF_GCLK_GEN_1_OE 0
131+
#define CONF_GCLK_GEN_1_OE 1
131132
#endif
132133

133134
// <q> Output Off Value
@@ -172,7 +173,7 @@
172173
// <i> This defines the clock source for generic clock generator 1
173174
// <id> gclk_gen_1_oscillator
174175
#ifndef CONF_GCLK_GEN_1_SRC
175-
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC32K
176+
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_DFLL48M
176177
#endif
177178
// </h>
178179

@@ -181,7 +182,7 @@
181182
// <i>
182183
// <id> gclk_gen_1_div
183184
#ifndef CONF_GCLK_GEN_1_DIV
184-
#define CONF_GCLK_GEN_1_DIV 1
185+
#define CONF_GCLK_GEN_1_DIV 150
185186
#endif
186187

187188
// </h>

‎ports/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -385,15 +385,15 @@
385385

386386
// <i> Select the clock source for DAC.
387387
#ifndef CONF_GCLK_DAC_SRC
388-
#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val
388+
#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK1_Val
389389
#endif
390390

391391
/**
392392
* \def CONF_GCLK_DAC_FREQUENCY
393393
* \brief DAC's Clock frequency
394394
*/
395395
#ifndef CONF_GCLK_DAC_FREQUENCY
396-
#define CONF_GCLK_DAC_FREQUENCY 48000000
396+
#define CONF_GCLK_DAC_FREQUENCY 320000
397397
#endif
398398

399399
// <y> USB Clock Source

‎ports/atmel-samd/asf4_conf/samd51/hpl_dac_config.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@
7272
// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us
7373
// <id> dac0_arch_refresh
7474
#ifndef CONF_DAC0_REFRESH
75-
#define CONF_DAC0_REFRESH 0
75+
#define CONF_DAC0_REFRESH 2
7676
#endif
7777
// </h>
7878
// <h> Channel 1 configuration
@@ -111,7 +111,7 @@
111111
// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us
112112
// <id> dac1_arch_refresh
113113
#ifndef CONF_DAC1_REFRESH
114-
#define CONF_DAC1_REFRESH 0
114+
#define CONF_DAC1_REFRESH 2
115115
#endif
116116
// </h>
117117

‎ports/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// Circuit Python SAMD51 clock tree:
22
// DFLL48M (with USBCRM on to sync with external USB ref) -> GCLK1, GCLK5
3-
// GCLK1 (48MHz) -> peripherals
4-
// GCLK5 (divided down to 2 MHz) -> DPLL0
3+
// GCLK1 (48MHz) -> 48 MHz peripherals
4+
// GCLK5 (48 MHz divided down to 2 MHz) -> DPLL0, DAC peripherals
55
// DPLL0 (multiplied up to 120 MHz) -> GCLK0, GCLK4 (output for monitoring)
66

77
// We'd like to use XOSC32K as a ref for DFLL48M on boards with a 32kHz crystal,

‎ports/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -73,15 +73,15 @@
7373
// <id> dac_gclk_selection
7474
// <i> Select the clock source for DAC.
7575
#ifndef CONF_GCLK_DAC_SRC
76-
#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
76+
#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK5_Val
7777
#endif
7878

7979
/**
8080
* \def CONF_GCLK_DAC_FREQUENCY
8181
* \brief DAC's Clock frequency
8282
*/
8383
#ifndef CONF_GCLK_DAC_FREQUENCY
84-
#define CONF_GCLK_DAC_FREQUENCY 48000000
84+
#define CONF_GCLK_DAC_FREQUENCY 2000000
8585
#endif
8686

8787
// <y> EVSYS Channel 0 Clock Source

‎ports/atmel-samd/common-hal/analogio/AnalogOut.c‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#include "atmel_start_pins.h"
3737
#include "hal/include/hal_dac_sync.h"
3838
#include "hpl/gclk/hpl_gclk_base.h"
39+
#include "peripheral_clk_config.h"
3940

4041
#ifdef SAMD21
4142
#include "hpl/pm/hpl_pm_base.h"
@@ -65,14 +66,16 @@ void common_hal_analogio_analogout_construct(analogio_analogout_obj_t* self,
6566

6667
#ifdef SAMD51
6768
hri_mclk_set_APBDMASK_DAC_bit(MCLK);
68-
hri_gclk_write_PCHCTRL_reg(GCLK, DAC_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK5_Val | (1 << GCLK_PCHCTRL_CHEN_Pos));
6969
#endif
7070

7171
#ifdef SAMD21
7272
_pm_enable_bus_clock(PM_BUS_APBC, DAC);
73-
_gclk_enable_channel(DAC_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val);
7473
#endif
7574

75+
// SAMD21: This clock should be <= 12 MHz, per datasheet section 47.6.3.
76+
// SAMD51: This clock should be <= 350kHz, per datasheet table 37-6.
77+
_gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC);
78+
7679
// Don't double init the DAC on the SAMD51 when both outputs are in use. We use the free state
7780
// of each output pin to determine DAC state.
7881
int32_t result = ERR_NONE;
@@ -123,7 +126,7 @@ void common_hal_analogio_analogout_deinit(analogio_analogout_obj_t *self) {
123126

124127
void common_hal_analogio_analogout_set_value(analogio_analogout_obj_t *self,
125128
uint16_t value) {
126-
// Input is 16 bit so make sure and set LEFTADJ to 1 to it takes the top
129+
// Input is 16 bit so make sure and set LEFTADJ to 1 so it takes the top
127130
// bits. This is currently done in asf4_conf/*/hpl_dac_config.h.
128131
dac_sync_write(&self->descriptor, self->channel, &value, 1);
129132
}

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