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docs/library/machine.SPI.rst
@@ -47,7 +47,7 @@ Methods
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- ``polarity`` can be 0 or 1, and is the level the idle clock line sits at.
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- ``phase`` can be 0 or 1 to sample data on the first or second clock edge
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respectively.
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- - ``bits`` is the width in bits of each transfer. Only 8 of is guaranteed to be supported by all hardware.
+ - ``bits`` is the width in bits of each transfer. Only 8 is guaranteed to be supported by all hardware.
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- ``firstbit`` can be ``SPI.MSB`` or ``SPI.LSB``.
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- ``pins`` is an optional tuple with the pins to assign to the SPI bus (deprecated, only for WiPy).
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- ``sck``, ``mosi``, ``miso`` are pins (machine.Pin) objects to use for bus signals. For most
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