Skip to content

Commit 1345093

Browse files
committed
stm32/qspi: Do an explicit read instead of using memory-mapped mode.
Using an explicit read eliminates the need to invalidate the D-cache after enabling the memory mapping mode, which takes additional time.
1 parent cc34b08 commit 1345093

1 file changed

Lines changed: 32 additions & 3 deletions

File tree

ports/stm32/qspi.c

Lines changed: 32 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ void qspi_init(void) {
4848

4949
QUADSPI->CR =
5050
2 << QUADSPI_CR_PRESCALER_Pos // F_CLK = F_AHB/3 (72MHz when CPU is 216MHz)
51+
| 3 << QUADSPI_CR_FTHRES_Pos // 4 bytes must be available to read/write
5152
#if defined(QUADSPI_CR_FSEL_Pos)
5253
| 0 << QUADSPI_CR_FSEL_Pos // FLASH 1 selected
5354
#endif
@@ -232,9 +233,37 @@ STATIC uint32_t qspi_read_cmd(void *self_in, uint8_t cmd, size_t len) {
232233

233234
STATIC void qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) {
234235
(void)self_in;
235-
// This assumes that cmd=0xeb
236-
qspi_memory_map();
237-
memcpy(dest, (void*)(0x90000000 + addr), len);
236+
QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
237+
238+
QUADSPI->DLR = len - 1; // number of bytes to read
239+
240+
QUADSPI->CCR =
241+
0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
242+
| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
243+
| 1 << QUADSPI_CCR_FMODE_Pos // indirect read mode
244+
| 3 << QUADSPI_CCR_DMODE_Pos // data on 4 lines
245+
| 4 << QUADSPI_CCR_DCYC_Pos // 4 dummy cycles
246+
| 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte
247+
| 3 << QUADSPI_CCR_ABMODE_Pos // alternate byte on 4 lines
248+
| 2 << QUADSPI_CCR_ADSIZE_Pos // 24-bit address size
249+
| 3 << QUADSPI_CCR_ADMODE_Pos // address on 4 lines
250+
| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
251+
| cmd << QUADSPI_CCR_INSTRUCTION_Pos // quad read opcode
252+
;
253+
254+
QUADSPI->ABR = 0; // alternate byte: disable continuous read mode
255+
QUADSPI->AR = addr; // addres to read from
256+
257+
// Read in the data
258+
while (len) {
259+
while (!(QUADSPI->SR & QUADSPI_SR_FTF)) {
260+
}
261+
*(uint32_t*)dest = QUADSPI->DR;
262+
dest += 4;
263+
len -= 4;
264+
}
265+
266+
QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
238267
}
239268

240269
const mp_qspi_proto_t qspi_proto = {

0 commit comments

Comments
 (0)