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24 | 24 | * THE SOFTWARE. |
25 | 25 | */ |
26 | 26 |
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27 | | -//TODO: Put stream/channel defs for i2c/spi/can, etc here |
| 27 | +// These are ordered by DMAx_Stream number, and within a stream by channel |
| 28 | +// number. The duplicate streams are ok as long as they aren't used at the |
| 29 | +// same time. |
| 30 | +// |
| 31 | +// Currently I2C and SPI are synchronous and they call dma_init/dma_deinit |
| 32 | +// around each transfer. |
| 33 | + |
| 34 | +// DMA1 streams |
| 35 | + |
| 36 | +#define DMA_STREAM_I2C1_RX DMA1_Stream0 |
| 37 | +#define DMA_CHANNEL_I2C1_RX DMA_CHANNEL_1 |
| 38 | + |
| 39 | +#define DMA_STREAM_SPI3_RX DMA1_Stream2 |
| 40 | +#define DMA_CHANNEL_SPI3_RX DMA_CHANNEL_0 |
| 41 | + |
| 42 | +#define DMA_STREAM_I2C3_RX DMA1_Stream2 |
| 43 | +#define DMA_CHANNEL_I2C3_RX DMA_CHANNEL_3 |
| 44 | + |
| 45 | +#define DMA_STREAM_I2C2_RX DMA1_Stream2 |
| 46 | +#define DMA_CHANNEL_I2C2_RX DMA_CHANNEL_7 |
| 47 | + |
| 48 | +#define DMA_STREAM_SPI2_RX DMA1_Stream3 |
| 49 | +#define DMA_CHANNEL_SPI2_RX DMA_CHANNEL_0 |
| 50 | + |
| 51 | +#define DMA_STREAM_SPI2_TX DMA1_Stream4 |
| 52 | +#define DMA_CHANNEL_SPI2_TX DMA_CHANNEL_0 |
| 53 | + |
| 54 | +#define DMA_STREAM_I2C3_TX DMA1_Stream4 |
| 55 | +#define DMA_CHANNEL_I2C3_TX DMA_CHANNEL_3 |
| 56 | + |
| 57 | +#define DMA_STREAM_DAC1 DMA1_Stream5 |
| 58 | +#define DMA_CHANNEL_DAC1 DMA_CHANNEL_7 |
| 59 | + |
| 60 | +#define DMA_STREAM_DAC2 DMA1_Stream6 |
| 61 | +#define DMA_CHANNEL_DAC2 DMA_CHANNEL_7 |
| 62 | + |
| 63 | +#define DMA_STREAM_SPI3_TX DMA1_Stream7 |
| 64 | +#define DMA_CHANNEL_SPI3_TX DMA_CHANNEL_0 |
| 65 | + |
| 66 | +#define DMA_STREAM_I2C1_TX DMA1_Stream7 |
| 67 | +#define DMA_CHANNEL_I2C1_TX DMA_CHANNEL_1 |
| 68 | + |
| 69 | +#define DMA_STREAM_I2C2_TX DMA1_Stream7 |
| 70 | +#define DMA_CHANNEL_I2C2_TX DMA_CHANNEL_7 |
| 71 | + |
| 72 | +// DMA2 streams |
| 73 | + |
| 74 | +#define DMA_STREAM_SPI1_RX DMA2_Stream2 |
| 75 | +#define DMA_CHANNEL_SPI1_RX DMA_CHANNEL_3 |
| 76 | + |
28 | 77 | #define DMA_STREAM_SDIO_RX DMA2_Stream3 |
29 | | -#define DMA_CHANNEL_SDIO_RX DMA_CHANNEL_4 |
| 78 | +#define DMA_CHANNEL_SDIO_RX DMA_CHANNEL_4 |
| 79 | + |
| 80 | +#define DMA_STREAM_SPI1_TX DMA2_Stream5 |
| 81 | +#define DMA_CHANNEL_SPI1_TX DMA_CHANNEL_3 |
30 | 82 |
|
31 | 83 | #define DMA_STREAM_SDIO_TX DMA2_Stream6 |
32 | | -#define DMA_CHANNEL_SDIO_TX DMA_CHANNEL_4 |
| 84 | +#define DMA_CHANNEL_SDIO_TX DMA_CHANNEL_4 |
33 | 85 |
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34 | 86 | typedef union { |
35 | 87 | uint16_t enabled; // Used to test if both counters are == 0 |
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