#ifndef __HW_GPRCM_H__

#define __HW_GPRCM_H__

#define GPRCM_O_APPS_SOFT_RESET 0x00000000

#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \

0x00000004

#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \

0x00000008

#define GPRCM_O_APPS_RESET_CAUSE \

0x0000000C

#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \

0x00000010

#define GPRCM_O_APPS_SRAM_DSLP_CFG \

0x00000018

#define GPRCM_O_APPS_SRAM_LPDS_CFG \

0x0000001C

#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \

0x00000020

#define GPRCM_O_TOP_DIE_ENABLE 0x00000100

#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \

0x00000104

#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \

0x00000108

#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C

#define GPRCM_O_APPS_GPIO_WAKE_CONF \

0x00000110

#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \

0x00000114

#define GPRCM_O_MEM_HCLK_DIV_CFG \

0x00000118

#define GPRCM_O_MEM_SYSCLK_DIV_CFG \

0x0000011C

#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \

0x00000120

#define GPRCM_O_NWP_SOFT_RESET 0x00000400

#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \

0x00000404

#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \

0x00000408

#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C

#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \

0x00000410

#define GPRCM_O_NWP_SRAM_DSLP_CFG \

0x00000418

#define GPRCM_O_NWP_SRAM_LPDS_CFG \

0x0000041C

#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \

0x00000420

#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \

0x00000424

#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \

0x00000428

#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \

0x0000042C

#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \

0x00000430

#define GPRCM_O_NWP_GPIO_WAKE_CONF \

0x00000434

#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \

0x00000438

#define GPRCM_O_GPRCM_DIEID_READ_REG5 \

0x00000448

#define GPRCM_O_GPRCM_DIEID_READ_REG6 \

0x0000044C

#define GPRCM_O_REF_FSM_CFG0 0x00000800

#define GPRCM_O_REF_FSM_CFG1 0x00000804

#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \

0x00000808

#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \

0x0000080C

#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \

0x00000810

#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \

0x00000814

#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \

0x00000818

#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \

0x0000081C

#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \

0x00000820

#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \

0x00000824

#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \

0x00000828

#define GPRCM_O_SPARE_RW0 0x0000082C

#define GPRCM_O_SPARE_RW1 0x00000830

#define GPRCM_O_APLLMCS_MCU_OVERRIDES \

0x00000834

#define GPRCM_O_SYSCLK_SWITCH_STATUS \

0x00000838

#define GPRCM_O_REF_LDO_CONTROLS \

0x0000083C

#define GPRCM_O_REF_RTRIM_CONTROL \

0x00000840

#define GPRCM_O_REF_SLICER_CONTROLS0 \

0x00000844

#define GPRCM_O_REF_SLICER_CONTROLS1 \

0x00000848

#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \

0x0000084C

#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \

0x00000850

#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \

0x00000854

#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \

0x00000858

#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \

0x0000085C

#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \

0x00000860

#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \

0x00000864

#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868

#define GPRCM_O_MEMSS_PWR_PS 0x0000086C

#define GPRCM_O_REF_FSM_DEBUG 0x00000870

#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \

0x00000874

#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \

0x00000878

#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \

0x0000087C

#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \

0x00000880

#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \

0x00000884

#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \

0x00000888

#define GPRCM_O_MEM_REF_FSM_CFG2 \

0x0000088C

#define GPRCM_O_TESTCTRL_POWER_CTRL \

0x00000C10

#define GPRCM_O_SSDIO_POWER_CTRL \

0x00000C14

#define GPRCM_O_MCSPI_N1_POWER_CTRL \

0x00000C18

#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C

#define GPRCM_O_WL_SDIO_POWER_CTRL \

0x00000C20

#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \

0x00000C24

#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \

0x00000C28

#define GPRCM_O_APPS_SECURE_INIT_DONE \

0x00000C30

#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \

0x00000C34

#define GPRCM_O_EN_APPS_REBOOT 0x00000C38

#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \

0x00000C3C

#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \

0x00000C40

#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \

0x00000C44

#define GPRCM_O_NWP_PWR_STATE 0x00000C48

#define GPRCM_O_APPS_PWR_STATE 0x00000C4C

#define GPRCM_O_MCU_PWR_STATE 0x00000C50

#define GPRCM_O_WTOP_PM_PS 0x00000C54

#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \

0x00000C58

#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \

0x00000C5C

#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \

0x00000C60

#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \

0x00000C64

#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \

0x00000C68

#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \

0x00000C6C

#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \

0x00000C70

#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \

0x00000C78

#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \

0x00000C7C

#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \

0x00000C80

#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \

0x00000C84

#define GPRCM_O_WTOP_MEM_RET_CFG \

0x00000C88

#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \

0x00000C8C

#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \

0x00000C90

#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \

0x00000C94

#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \

0x00000C98

#define GPRCM_O_DCDC_CLK_GEN_CONFIG \

0x00000C9C

#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \

0x00000CA0

#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \

0x00000CA4

#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \

0x00000CA8

#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \

0x00000CAC

#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \

0x00000CB0

#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \

0x00000CB4

#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \

0x00000CB8

#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \

0x00000CBC

#define GPRCM_O_GPRCM_DIEID_READ_REG0 \

0x00000CC0

#define GPRCM_O_GPRCM_DIEID_READ_REG1 \

0x00000CC4

#define GPRCM_O_GPRCM_DIEID_READ_REG2 \

0x00000CC8

#define GPRCM_O_GPRCM_DIEID_READ_REG3 \

0x00000CCC

#define GPRCM_O_GPRCM_DIEID_READ_REG4 \

0x00000CD0

#define GPRCM_O_APPS_SS_OVERRIDES \

0x00000CD4

#define GPRCM_O_NWP_SS_OVERRIDES \

0x00000CD8

#define GPRCM_O_SHARED_SS_OVERRIDES \

0x00000CDC

#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \

0x00000CE0

#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \

0x00000CE4

#define GPRCM_O_MCU_PSCON_OVERRIDES \

0x00000CE8

#define GPRCM_O_WTOP_PSCON_OVERRIDES \

0x00000CEC

#define GPRCM_O_WELP_PSCON_OVERRIDES \

0x00000CF0

#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \

0x00000CF4

#define GPRCM_O_MCSPI_PSCON_OVERRIDES \

0x00000CF8

#define GPRCM_O_SSDIO_PSCON_OVERRIDES \

0x00000CFC

#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \

0x00000002 // Soft-reset1 for APPS : Cortex

// sysrstn is asserted and in

// addition to that the associated

// APPS Peripherals are also reset.

// This is an auto-clear bit.

#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \

0x00000001 // Soft-reset0 for APPS : Only

// sys-resetn for Cortex will be

// asserted. This is an auto-clear

// bit.

#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \

0x000000FF // Mask for LPDS Wakeup interrupt :

// [7] - Host IRQ from NWP [6] -

// NWP_LPDS_Wake_irq (TRUE_LPDS) [5]

// - NWP Wake-request to APPS [4] -

// GPIO [3:1] - Reserved [0] - LPDS

// Wakeup-timer

#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0

#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \

0x000000FF // Indicates the cause for wakeup

// from LPDS : [7] - Host IRQ from

// NWP [6] - NWP_LPDS_Wake_irq

// (TRUE_LPDS) [5] - NWP

// Wake-request to APPS [4] - GPIO

// [3:1] - Reserved [0] - LPDS

// Wakeup-timer

#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0

#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \

0x000000FF // Indicates the reset cause for

// APPS : "0000" - Wake from HIB/OFF

// mode; "0001" - Wake from LPDS ;

// "0010" - Reserved ; "0011" -

// Soft-reset0 (Only APPS

// Cortex-sysrstn is asserted);

// "0100" - Soft-reset1 (APPS

// Cortex-sysrstn and APPS

// peripherals are reset); "0101" -

// WDOG0 (APPS Cortex-sysrstn and

// APPS peripherals are reset);

// "0110" - MCU Soft-reset (APPS +

// NWP Cortex-sysrstn + Peripherals

// are reset); "0111" - Secure Init

// done (Indication that reset has

// happened after DevInit); "1000" -

// Dev Mode Patch Init done (During

// development mode, patch

// downloading and Cortex

// re-vectoring is completed)

#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0

#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \

0xFFFFFFFF // OPP Request Configuration

// (Number of slow-clk cycles) for

// LPDS Wake-timer : This

// configuration implies the RTC

// time-stamp, which must be few

// slow-clks prior to

// APPS_LPDS_WAKETIME_WAKE_CFG, such

// that by the time actual wakeup is

// given, OPP is already switched to

// ACTIVE (RUN).

#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0

#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \

0x000FFFFF // Configuration of APPS Memories

// during Deep-sleep : 0 - SRAMs are

// OFF ; 1 - SRAMs are Retained.

// APPS SRAM Cluster information :

// [0] - 1st column in MEMSS

// (Applicable only when owned by

// APPS); [1] - 2nd column in MEMSS

// (Applicable only when owned by

// APPS); [2] - 3rd column in MEMSS

// (Applicable only when owned by

// APPS) ; [3] - 4th column in MEMSS

// (Applicable only when owned by

// APPS) ; [16] - MCU-PD - Apps

// cluster 0 (TBD); [19:18] -

// Reserved.

#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0

#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \

0x000FFFFF // Configuration of APPS Memories

// during LPDS : 0 - SRAMs are OFF ;

// 1 - SRAMs are Retained. APPS SRAM

// Cluster information : [0] - 1st

// column in MEMSS (Applicable only

// when owned by APPS); [1] - 2nd

// column in MEMSS (Applicable only

// when owned by APPS); [2] - 3rd

// column in MEMSS (Applicable only

// when owned by APPS) ; [3] - 4th

// column in MEMSS (Applicable only

// when owned by APPS) ; [16] -

// MCU-PD - Apps cluster 0 (TBD);

// [19:18] - Reserved.

#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0

#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \

0xFFFFFFFF // Configuration (in no of

// slow_clks) which says when the

// actual wakeup request for

// removing the PD-reset be given.

#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0

#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \

0x00001000

#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \

0x00000F00

#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8

#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \

0x00000002 // 1 - Top-die is enabled ;

#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \

0x00000001 // 1 - Enable the top-die ; 0 -

// Disable the top-die

#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \

0xF0000000 // Configuration (in slow_clks) for

// number of clks between

// Flash-3p3-rstn to D2D POR Resetn.

#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28

#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \

0x00FF0000 // Configuration (in slow_clks) for

// number of clks between Top-die

// Switch-Enable and Top-die Flash

// 3p3 Reset removal

#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16

#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \

0x000000FF // Configuration (in slow_clks) for

// number of clks between D2D POR

// Reset removal and bottom die FMC

// reset removal

#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0

#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \

0x00000001 // 1 - Assert the global reset for

// MCU (APPS + NWP) ; Asserts both

// Cortex sysrstn and its

// peripherals 0 - Deassert the

// global reset for MCU (APPS + NWP)

// ; Asserts both Cortex sysrstn and

// its peripherals Note : Reset for

// shared peripherals is not

// affected here.

#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \

0x000007C0 // Configuration (in number of 38.4

// MHz clks) for the OFF-Time in

// generation of ADC_CLK

#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6

#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \

0x0000003E // Configuration (in number of 38.4

// MHz clks) for the ON-Time in

// generation of ADC_CLK

#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1

#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \

0x00000001 // 1 - Enable the ADC_CLK ; 0 -

// Disable the ADC_CLK

#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \

0x00000003 // "00" - Wake on Level0 on

// selected GPIO pin (GPIO is

// selected inside the HIB3p3

// module); "01" - Wakeup on

// fall-edge of GPIO pin.

#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0

#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \

0xFFFFFFFE

#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1

#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \

0x00000001 // 1 - Override the secure-mode

// done for booting up NWP (Wakeup

// NWP on its event independent of

// CM4 state) ; 0 - Donot override

// the secure-mode done for NWP boot

// (NWP must be enabled by CM4 only)

#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \

0x00000007 // Division configuration for

// HCLKDIVOUT : "000" - Divide by 1

// ; "001" - Divide by 2 ; "010" -

// Divide by 3 ; "011" - Divide by 4

// ; "100" - Divide by 5 ; "101" -

// Divide by 6 ; "110" - Divide by 7

// ; "111" - Divide by 8

#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0

#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \

0x00000038

#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3

#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \

0x00000007

#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0

#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \

0x0000FF00

#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8

#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \

0x000000FF

#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0

#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \

0x00000002 // Soft-reset1 for NWP - Cortex

// sysrstn and NWP associated

// peripherals are - This is an

// auto-clr bit.

#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \

0x00000001 // Soft-reset0 for NWP - Only

// Cortex-sysrstn is asserted - This

// is an auto-clear bit.

#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \

0x000000FF // Mask for LPDS Wakeup interrupt :

// 7 - WLAN Host Interrupt ; 6 -

// WLAN to NWP Wake request ; 5 -

// APPS to NWP Wake request; 4 -

// GPIO Wakeup ; 3 - Autonomous UART

// Wakeup ; 2 - SSDIO Wakeup ; 1 -

// Autonomous SPI Wakeup ; 0 - LPDS

// Wakeup-timer

#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0

#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \

0x000000FF // Indicates the cause for NWP

// LPDS-Wakeup : 7 - WLAN Host

// Interrupt ; 6 - WLAN to NWP Wake

// request ; 5 - APPS to NWP Wake

// request; 4 - GPIO Wakeup ; 3 -

// Autonomous UART Wakeup ; 2 -

// SSDIO Wakeup ; 1 - Autonomous SPI

// Wakeup ; 0 - LPDS Wakeup-timer

#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0

#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \

0x000000FF // Indicates the reset cause for

// NWP : "0000" - Wake from HIB/OFF

// mode; "0001" - Wake from LPDS ;

// "0010" - Reserved ; "0011" -

// Soft-reset0 (Only NWP

// Cortex-sysrstn is asserted);

// "0100" - Soft-reset1 (NWP

// Cortex-sysrstn and NWP

// peripherals are reset); "0101" -

// WDOG0 (NWP Cortex-sysrstn and NWP

// peripherals are reset); "0110" -

// MCU Soft-reset (APPS + NWP

// Cortex-sysrstn + Peripherals are

// reset); "0111" - SSDIO Function2

// reset (Only Cortex-sysrstn is

// asserted) ; "1000" - Reset due to

// WDOG of APPS (NWP Cortex-sysrstn

// and NWP peripherals are reset);

#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0

#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \

0xFFFFFFFF // OPP Request Configuration

// (Number of slow-clk cycles) for

// LPDS Wake-timer

#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0

#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \

0x000FFFFF // Configuration of NWP Memories

// during DSLP : 0 - SRAMs are OFF ;

// 1 - SRAMs are Retained. NWP SRAM

// Cluster information : [2] - 3rd

// column in MEMSS (Applicable only

// when owned by NWP) ; [3] - 4th

// column in MEMSS (Applicable only

// when owned by NWP) ; [4] - 5th

// column in MEMSS (Applicable only

// when owned by NWP) ; [5] - 6th

// column in MEMSS (Applicable only

// when owned by NWP) ; [6] - 7th

// column in MEMSS (Applicable only

// when owned by NWP) ; [7] - 8th

// column in MEMSS (Applicable only

// when owned by NWP) ; [8] - 9th

// column in MEMSS (Applicable only

// when owned by NWP) ; [9] - 10th

// column in MEMSS (Applicable only

// when owned by NWP) ; [10] - 11th

// column in MEMSS (Applicable only

// when owned by NWP) ; [11] - 12th

// column in MEMSS (Applicable only

// when owned by NWP) ; [12] - 13th

// column in MEMSS (Applicable only

// when owned by NWP) ; [13] - 14th

// column in MEMSS (Applicable only

// when owned by NWP) ; [14] - 15th

// column in MEMSS (Applicable only

// when owned by NWP) ; [19:18] -

// Reserved.

#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0

#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \

0x000FFFFF // Configuration of NWP Memories

// during LPDS : 0 - SRAMs are OFF ;

// 1 - SRAMs are Retained. NWP SRAM

// Cluster information : [2] - 3rd

// column in MEMSS (Applicable only

// when owned by NWP) ; [3] - 4th

// column in MEMSS (Applicable only

// when owned by NWP) ; [4] - 5th

// column in MEMSS (Applicable only

// when owned by NWP) ; [5] - 6th

// column in MEMSS (Applicable only

// when owned by NWP) ; [6] - 7th

// column in MEMSS (Applicable only

// when owned by NWP) ; [7] - 8th

// column in MEMSS (Applicable only

// when owned by NWP) ; [8] - 9th

// column in MEMSS (Applicable only

// when owned by NWP) ; [9] - 10th

// column in MEMSS (Applicable only

// when owned by NWP) ; [10] - 11th

// column in MEMSS (Applicable only

// when owned by NWP) ; [11] - 12th

// column in MEMSS (Applicable only

// when owned by NWP) ; [12] - 13th

// column in MEMSS (Applicable only

// when owned by NWP) ; [13] - 14th

// column in MEMSS (Applicable only

// when owned by NWP) ; [14] - 15th

// column in MEMSS (Applicable only

// when owned by NWP) ; [19:18] -

// Reserved.

#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0

#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \

0xFFFFFFFF // Wake time configuration (no of

// slow clks) for NWP wake from

// LPDS.

#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0

#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \

0xFFFE0000

#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17

#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \

0x00010000 // 0 - APPS is selected as host for

// Autonms SPI ; 1 - External host

// is selected as host for Autonms

// SPI

#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \

0x00010000

#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \

0x00000002 // When 1 => IDLE-mode is

// acknowledged by the SPI-IP. (This

// is for MCSPI_N1)

#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \

0x00000001 // When 1 => Request for IDLE-mode

// for autonomous SPI. (This is for

// MCSPI_N1)

#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \

0x00000001 // 1 - Request for waking up NWP

// from any of its low-power modes

// (SLP/DSLP/LPDS)

#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \

0x00000001 // 1 - Request for wakinp up WLAN

// from its ELP Mode (This gets

// triggered to ELP-logic of WLAN)

#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \

0x00000003 // "00" - Wakeup on level0 of the

// selected GPIO (GPIO gets selected

// inside HIB3P3-module); "01" -

// Wakeup on fall-edge of selected

// GPIO.

#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0

#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \

0x0000FFFF // This corrsponds to ROW_32

// [31:16] of the FUSEFARM. SPARE

#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0

#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \

0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM

// : [5:0] - ADC OFFSET ; [13:6] -

// TEMP_SENSE ; [14:14] - DFT_GSG ;

// [15:15] - FMC_DISABLE ; [31:16] -

// WLAN_MAC ID

#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0

#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \

0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM

// : [31:0] : WLAN MAC ID

#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0