docs: 'The DSL is compute' — architecture principle for memory-free network definitions - #1194

New explanation page explanation/dsl-principles.adoc, linked from the architecture document's solution strategy and the nav.

It writes down the principle the recent work kept proving implicitly, so it can be taught instead of re-derived:

A network definition is a pure description of computation. Every claim about memory, encoding, layout, or placement lives outside the DSL — and every such claim is either honored by a mechanism or visibly rejected. Never silently approximated.

Contents:

• the level-responsibility table (DSL → Format → WeightForm → Plan → Resolvers → Dispatch), with the rule that information flows strictly downward;
• evidence: Ternary f32 LUT gemv — vendored NeoGPU kernel: exact FP32×b1.58 matmul for baseline-NEON ARM (Pi-4/A72) #1136 (new ternary arithmetic, zero DSL change) and Packed-tensor mapped staging: serve Q4_K/Q6_K/ternary blocks straight from the mmap on Android #1189/feat(#1189): packed-tensor mapped staging — Q4_K/Q6_K served straight from the mmap on Android #1190 (1 GB model under a 256 MB ART cap, zero DSL change) — plus the planner-lie counterexample from feat(#1189): packed-tensor mapped staging — Q4_K/Q6_K served straight from the mmap on Android #1190 as the reason claims must be contracts, not hints;
• what the principle rules out (memory annotations in network definitions, is-ladders in ops, runtime memory policy, silent fallbacks);
• where knobs actually belong, and why defaults deserve the investment over override surface.

Docs only — no code changes.

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