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@@ -30,7 +30,7 @@ Detailed analyzer results are written as XML to the file that is specified by `f
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Turns off analyzer output to the **Output** window.
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/analyze:stacksize`number`
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The `number` parameter that is used with this option specifies the size, in bytes, of the stack frame for which warning [C6262](/visualstudio/code-quality/c6262) is generated. If this parameter is not specified, the stack frame size is 16KB by default.
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The `number` parameter that is used with this option specifies the size, in bytes, of the stack frame for which warning [C6262](/visualstudio/code-quality/c6262) is generated. The space before `number` is optional. If this parameter is not specified, the stack frame size is 16KB by default.
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/analyze:max_paths`number`
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The `number` parameter that is used with this option specifies the maximum number of code paths to be analyzed. If this parameter is not specified, the number is 256 by default. Larger values perform more thorough checking, but the analysis might take longer.
Copy file name to clipboardExpand all lines: docs/build/reference/arch-x64.md
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---
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title: "/arch (x64)"
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ms.date: "11/04/2016"
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ms.date: "10/01/2019"
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ms.assetid: ecda22bf-5bed-43f4-99fb-88aedd83d9d8
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---
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# /arch (x64)
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## Syntax
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```
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/arch:[AVX|AVX2]
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/arch:[AVX|AVX2|AVX512]
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```
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## Arguments
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**/arch:AVX2**<br/>
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Enables the use of Intel Advanced Vector Extensions 2 instructions.
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**/arch:AVX512**<br/>
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Enables the use of Intel Advanced Vector Extensions 512 instructions.
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## Remarks
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The **/arch** option enables the use of certain instruction set extensions, particularly for vector calculation, available in processors from Intel and AMD. In general, more recently introduced processors may support additional extensions over those supported by older processors, although you should consult the documentation for a particular processor or test for instruction set extension support using [__cpuid](../../intrinsics/cpuid-cpuidex.md) before executing code using an instruction set extension.
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**/arch** only affects code generation for native functions. When you use [/clr](clr-common-language-runtime-compilation.md) to compile, **/arch** has no effect on code generation for managed functions.
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The `__AVX__` preprocessor symbol is defined when the **/arch:AVX** compiler option is specified. The `__AVX2__` preprocessor symbol is defined when the **/arch:AVX2** compiler option is specified. For more information, see [Predefined Macros](../../preprocessor/predefined-macros.md). The **/arch:AVX2** option was introduced in Visual Studio 2013 Update 2, version 12.0.34567.1.
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The processor extensions have the following characteristics:
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- The default mode uses SSE2 instructions for scalar floating-point and vector calculations. These instructions allow calculation with 128-bit vectors of single-precision, double-precision and 1, 2, 4 or 8 byte integer values, as well as single-precision and double-precision scalar floating-point values.
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-**AVX** introduced an alternative instruction encoding for vector and floating-point scalar instructions that allows vectors of either 128 bits or 256 bits, and zero-extends all vector results to the full vector size. (For legacy compatibility, SSE-style vector instructions preserve all bits beyond bit 127.) Most floating-point operations are extended to 256 bits.
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-**AVX2** extends most integer operations to 256-bit vectors and enables use of Fused Multiply-Add (FMA) instructions.
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-**AVX-512** introduced another instruction encoding form that allows 512-bit vectors, plus certain other optional features. Instructions for additional operations were also added.
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Each **/arch** option may also enable the use of other non-vector instructions that are associated with that option. An example is the use of certain BMI instructions when **/arch:AVX2** is specified.
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The `__AVX__` preprocessor symbol is defined when the **/arch:AVX**, **/arch:AVX2** or **/arch:AVX512** compiler option is specified. The `__AVX2__` preprocessor symbol is defined when the **/arch:AVX2** or **/arch:AVX512** compiler option is specified. The `__AVX512F__`, `__AVX512CD__`, `__AVX512BW__`, `__AVX512DQ__` and `__AVX512VL__` preprocessor symbols are defined when the **/arch:AVX512** compiler option is specified. For more information, see [Predefined Macros](../../preprocessor/predefined-macros.md). The **/arch:AVX2** option was introduced in Visual Studio 2013 Update 2, version 12.0.34567.1. Limited support for **/arch:AVX512** was added in Visual Studio 2017, and expanded in Visual Studio 2019.
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### To set the /arch:AVXor /arch:AVX2 compiler option in Visual Studio
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### To set the /arch:AVX, /arch:AVX2or /arch:AVX512 compiler option in Visual Studio
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1. Open the **Property Pages** dialog box for the project. For more information, see [Set C++ compiler and build properties in Visual Studio](../working-with-project-properties.md).
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1. Select the **Configuration Properties**, **C/C++** folder.
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1. Select the **Code Generation** property page.
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1. In the **Enable Enhanced Instruction Set** drop-down box, choose **Advanced Vector Extensions (/arch:AVX)** or **Advanced Vector Extensions 2 (/arch:AVX2)**.
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1. In the **Enable Enhanced Instruction Set** drop-down box, choose **Advanced Vector Extensions (/arch:AVX)**, **Advanced Vector Extensions 2 (/arch:AVX2)** or **Advanced Vector Extensions 512 (/arch:AVX512)**.
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title: "/arch (x86)"
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ms.date: "11/04/2016"
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ms.date: "10/01/2019"
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# /arch (x86)
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## Syntax
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```
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/arch:[IA32|SSE|SSE2|AVX|AVX2]
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/arch:[IA32|SSE|SSE2|AVX|AVX2|AVX512]
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```
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## Arguments
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**/arch:AVX2**<br/>
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Enables the use of Intel Advanced Vector Extensions 2 instructions.
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**/arch:AVX512**<br/>
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Enables the use of Intel Advanced Vector Extensions 512 instructions.
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## Remarks
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The SSE and SSE2 instructions exist on various Intel and AMD processors. The AVX instructions exist on Intel Sandy Bridge processors and AMD Bulldozer processors. AVX2 instructions are supported by Intel Haswell and Broadwell processors and AMD Excavator-based processors.
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The **/arch** option enables or disables the use of certain instruction set extensions, particularly for vector calculation, available in processors from Intel and AMD. In general, more recently introduced processors may support additional extensions over those supported by older processors, although you should consult the documentation for a particular processor or test for instruction set extension support using [__cpuid](../../intrinsics/cpuid-cpuidex.md) before executing code using an instruction set extension.
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**/arch** only affects code generation for native functions. When you use [/clr](clr-common-language-runtime-compilation.md) to compile, **/arch** has no effect on code generation for managed functions.
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The `_M_IX86_FP`, `__AVX__` and `__AVX2__` macros indicate which, if any, **/arch**compiler option was used. For more information, see [Predefined Macros](../../preprocessor/predefined-macros.md). The **/arch:AVX2** option and `__AVX2__` macro were introduced in Visual Studio 2013 Update 2, version 12.0.34567.1.
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The **/arch**options refer to instruction set extensions with the following characteristics:
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The optimizer chooses when and how to use the SSE and SSE2 instructions when **/arch** is specified. It uses SSE and SSE2 instructions for some scalar floating-point computations when it determines that it is faster to use the SSE/SSE2 instructions and registers instead of the x87 floating-point register stack. As a result, your code may actually use a mixture of both x87 and SSE/SSE2 for floating-point computations. Also, with **/arch:SSE2**, SSE2 instructions can be used for some 64-bit integer operations.
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-**IA32** is the legacy 32-bit x86 instruction set without any vector operations and using x87 for floating-point calculations.
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In addition to using the SSE and SSE2 instructions, the compiler also uses other instructions that are present on the processor revisions that support SSE and SSE2. An example is the CMOV instruction that first appeared on the Pentium Pro revision of the Intel processors.
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-**SSE** allows calculation with vectors of up to four single-precision floating-point values. Corresponding scalar floating-point instructions were added as well.
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Because the x86 compiler generates code that uses SSE2 instructions by default, you must specify **/arch:IA32** to disable generation of SSE and SSE2 instructions for x86 processors.
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-**SSE2** allows calculation with 128-bit vectors of single-precision, double-precision and 1, 2, 4 or 8 byte integer values. Double-precision scalar instructions were also added.
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**/arch** only affects code generation for native functions. When you use [/clr](clr-common-language-runtime-compilation.md) to compile, **/arch** has no effect on code generation for managed functions.
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-**AVX** introduced an alternative instruction encoding for vector and floating-point scalar instructions that allows vectors of either 128 bits or 256 bits, and zero-extends all vector results to the full vector size. (For legacy compatibility, SSE-style vector instructions preserve all bits beyond bit 127.) Most floating-point operations are extended to 256 bits.
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-**AVX2** extends most integer operations to 256-bit vectors, and enables use of Fused Multiply-Add (FMA) instructions.
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-**AVX512** introduced another instruction encoding form that allows 512-bit vectors, plus certain other optional features. Instructions for additional operations were also added.
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The optimizer chooses when and how to use vector instructions depending on which **/arch** is specified. Scalar floating-point computations are performed with SSE or AVX instructions when available. Some calling conventions specify passing floating-point arguments on the x87 stack, and as a result, your code may use a mixture of both x87 and SSE/AVX instructions for floating-point computations. Integer vector instructions can also be used for some 64-bit integer operations when available.
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**/arch** and [/QIfist](qifist-suppress-ftol.md) cannot be used on the same compiland. In particular, if you do not use `_controlfp` to modify the FP control word, then the run-time startup code sets the x87 FPU control word precision-control field to 53-bits. Therefore, every float and double operation in an expression uses a 53-bit significand and a 15-bit exponent. However, every SSE single-precision operation uses a 24-bit significand and an 8-bit exponent, and SSE2 double-precision operations use a 53-bit significand and an 11-bit exponent. For more information, see [_control87, _controlfp, \__control87_2](../../c-runtime-library/reference/control87-controlfp-control87-2.md). These differences are possible in one expression tree, but not in cases where a user assignment is involved after each subexpression. Consider the following:
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In addition to the vector and floating-point scalar instructions, each **/arch** option may also enable the use of other non-vector instructions that are associated with that option. An example is the CMOVcc instruction family that first appeared on the Intel Pentium Pro processors. Because SSE instructions were introduced with the subsequent Intel Pentium III processor, CMOVcc instructions may be generated except when **/arch:IA32** is specified.
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Floating-point operations are normally rounded to double-precision (64-bit) in x87 code, but you can use `_controlfp` to modify the FP control word, including setting the precision control to extended precision (80-bit) or single-precision (32-bit). For more information, see [_control87, _controlfp, \__control87_2](../../c-runtime-library/reference/control87-controlfp-control87-2.md). SSE and AVX have separate single-precision and double-precision instructions for each operation, so there is no equivalent for SSE/AVX code. This can change how results are rounded when the result of a floating-point operation is used directly in further calculation instead of assigning it to a user variable. Consider the following:
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```cpp
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r = f1 * f2 + d; // Different results are possible on SSE/SSE2.
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```
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Compare:
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With explicit assignment:
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```cpp
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t = f1 * f2; // Do f1 * f2, round to the type of t.
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r = t + d; // This should produce the same overall result
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// whether x87 stack is used or SSE/SSE2 is used.
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```
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### To set this compiler option for AVX, AVX2, IA32, SSE, or SSE2 in Visual Studio
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**/arch** and [/QIfist](qifist-suppress-ftol.md) cannot be used on the same compiland. The **/QIfist** option changes the rounding behavior of floating-point to integer conversion. The default behavior is to truncate (round toward zero), whereas the **/QIfist** option specifies use of the floating-point environment rounding mode. Because this changes the behavior of all floating-point to integer conversions, this flag has been deprecated. When compiling for SSE or AVX you can round a floating-point value to an integer using the floating-point environment rounding mode by using an intrinsic function sequence:
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```cpp
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intconvert_float_to_int(float x) {
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return _mm_cvtss_si32(_mm_set_ss(x));
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}
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int convert_double_to_int(double x) {
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return _mm_cvtsd_si32(_mm_set_sd(x));
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}
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```
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The `_M_IX86_FP`, `__AVX__`, `__AVX2__`, `__AVX512F__`, `__AVX512CD__`, `__AVX512BW__`, `__AVX512DQ__` and `__AVX512VL__` macros indicate which, if any, **/arch** compiler option was used. For more information, see [Predefined Macros](../../preprocessor/predefined-macros.md). The **/arch:AVX2** option and `__AVX2__` macro were introduced in Visual Studio 2013 Update 2, version 12.0.34567.1. Limited support for **/arch:AVX512** was added in Visual Studio 2017, and expanded in Visual Studio 2019.
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### To set this compiler option for AVX, AVX2, AVX512, IA32, SSE, or SSE2 in Visual Studio
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1. Open the **Property Pages** dialog box for the project. For more information, see [Set C++ compiler and build properties in Visual Studio](../working-with-project-properties.md).
Represents a *map*, which is a collection of key-value pairs.
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Represents a *map*, which is a collection of key-value pairs. Implements [Windows::Foundation::Collections::IObservableMap](/uwp/api/windows.foundation.collections.iobservablemap_k_v_) to help with XAML [data binding](/windows/uwp/data-binding/data-binding-in-depth).
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## Syntax
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Represents a sequential collection of objects that can be individually accessed by index.
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Represents a sequential collection of objects that can be individually accessed by index. Implements [Windows::Foundation::Collections::IObservableVector](/uwp/api/Windows.Foundation.Collections.IObservableVector_T_) to help with XAML [data binding](/windows/uwp/data-binding/data-binding-in-depth).
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## Syntax
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