Single-Cycle RISC-V Processor (RV32I)

A fully functional single-cycle RISC-V processor implemented in Verilog, supporting all 37 base integer (RV32I) instructions. Built for learning and FPGA prototyping.

├── rtl/
│   ├── core/
│   │   ├── processor.v          # Top-level datapath (connects all modules)
│   │   ├── PC.v                 # Program counter register
│   │   ├── PC_adder.v           # PC + 4 adder
│   │   ├── register_file.v      # 32 x 32-bit register file
│   │   └── imm_gen.v            # Immediate generator for all formats
│   ├── control/
│   │   └── main_control_unit.v  # Opcode decoder → control signals
│   ├── execution/
│   │   ├── ALU.v                # 10-operation ALU
│   │   └── ALU_control_unit.v   # ALUOp + funct3/funct7 → ALU select
│   ├── memory/
│   │   ├── instruction_mem.v    # Instruction ROM (loads program.mem)
│   │   ├── data_memory.v        # Data RAM with byte/half/word access
│   │   └── data.mem             # Initial data memory contents
│   └── utils/
│       ├── adder.v              # Generic 32-bit adder
│       ├── mux.v                # 2-to-1 multiplexer
│       └── mux4to1.v            # 4-to-1 multiplexer
├── sim/
│   └── tb_processor.v           # Testbench with debug signal outputs
├── demo_programs/
│   ├── bubble_sort/program.mem  # Bubble sort demo (default)
│   └── sum_of_n_natural_nums/program.mem
├── fpga/
│   └── constraints/constraints.xdc  # Pin constraints (Zynq/Zedboard-style)
└── images/

Each clock cycle executes one instruction through the full datapath:

1. Fetch — PC addresses instruction memory; PC+4 is computed in parallel.
2. Decode — Opcode drives the main control unit; the immediate generator sign-extends fields; register file reads rs1 and rs2.
3. Execute — ALU performs the operation selected by the ALU control unit. Source muxes choose between register values, PC, zero, or immediates.
4. Memory — Data memory performs load/store with byte, halfword, or word granularity based on funct3.
5. Write-back — A 4-to-1 mux selects the write-back value: ALU result, memory read data, or PC+4 (for JAL/JALR).
6. Next PC — A 4-to-1 mux picks the next PC from: PC+4, branch target, JAL target, or JALR target.

The default demo program sorts a 5-element array in data memory using bubble sort.

Program: demo_programs/bubble_sort/program.mem

The assembly initializes data memory with the values {2, 3, 9, 1, 5}, then runs nested loops to sort them in ascending order using compare-and-swap.

1. Open sim/tb_processor.v in your simulator (Vivado, ModelSim, etc.).
2. The instruction memory automatically loads program.mem.
3. Run the simulation — all debug signals (PC, instruction, control signals, ALU result, branch decisions) are exposed as top-level outputs for waveform inspection.

The design is constrained for an FPGA board with 8 LEDs and a toggle switch.

• Switch (SW): selects what is displayed on the LEDs — toggle between the program counter value and control signals.
• LEDs [7:0]: show the selected view.
• Reset button: resets the processor to PC = 0.

Pin assignments are defined in fpga/constraints/constraints.xdc.