[None][doc] Update DS-R1 example doc #9231
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Signed-off-by: jiahanc <173873397+jiahanc@users.noreply.github.com>
📝 WalkthroughWalkthroughUpdated the Deepseek V3 README with configuration modifications to disable CUDA block reuse and increase maximum batch size from 1024 to 2048 across multiple example configurations. Changes
Estimated code review effort🎯 1 (Trivial) | ⏱️ ~3 minutes
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🧹 Nitpick comments (2)
examples/models/core/deepseek_v3/README.md (2)
245-245: Add brief comment explainingenable_block_reuse: falsefor clarity.The
enable_block_reuse: falsesetting aligns with the PR objective to disable KV reuse (documented at line 838). However, users reading these example configurations may benefit from an inline comment explaining why this is disabled and when they should consider using it. Consider adding a comment like:cuda_graph_config: enable_padding: true enable_block_reuse: false # Disabled for benchmarking stability; see KV Cache Reuse section max_batch_size: 1024
309-309: Aligntrtllm-servedefault with configuration examples.Increasing
--max_batch_sizefrom 1024 to 2048 aligns with the FP4 max-throughput config change (line 260). However, this is now the default for the API server example, which may surprise users expecting lower default batch sizes for latency-sensitive workloads. Consider clarifying in nearby documentation that users should adjust--max_batch_sizebased on their use case (e.g., lower for latency, higher for throughput). Alternatively, add a comment in the example explaining this is a throughput-oriented default.
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🧠 Learnings (2)
📚 Learning: 2025-08-14T06:36:40.701Z
Learnt from: timlee0212
Repo: NVIDIA/TensorRT-LLM PR: 6886
File: tensorrt_llm/_torch/models/modeling_deepseekv3.py:0-0
Timestamp: 2025-08-14T06:36:40.701Z
Learning: In DeepSeek V3 model (tensorrt_llm/_torch/models/modeling_deepseekv3.py), the disagreement between AllReduce.__init__ guard and _compute_mlp_tp_size logic for MNNVL usage is expected by design. The AllReduce component and MLP TP-size computation intentionally use different criteria for MNNVL availability decisions.
Applied to files:
examples/models/core/deepseek_v3/README.md
📚 Learning: 2025-09-04T07:33:10.618Z
Learnt from: MrGeva
Repo: NVIDIA/TensorRT-LLM PR: 7219
File: tensorrt_llm/_torch/auto_deploy/compile/backends/torch_cudagraph.py:162-168
Timestamp: 2025-09-04T07:33:10.618Z
Learning: When users explicitly provide cuda_graph_batch_sizes in TorchCudagraphCompiler, respect their choices and only sanitize the values (clamp, dedupe, sort) without forcing additional batch sizes like 1 or max_batch_size. Only add commonly-used batch sizes when falling back to the heuristic.
Applied to files:
examples/models/core/deepseek_v3/README.md
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🔇 Additional comments (4)
examples/models/core/deepseek_v3/README.md (4)
259-260: Verify increased batch size doesn't trigger OOM in practical use.The max_batch_size is increased from 1024 to 2048 for the max-throughput configuration. While this supports higher throughput, the documentation at line 317 already warns of possible OOM issues with max-throughput configs. Ensure this batch size increase has been validated on B200 hardware and update the OOM mitigation guidance if needed.
273-274: Configuration is consistent with FP4 min-latency counterpart.The
enable_block_reuse: falseaddition here mirrors line 245, maintaining consistency across precision variants. The lower max_batch_size (1024) for min-latency is appropriate.
289-292: Verify FP8 max-throughput batch size configuration.This section sets
max_batch_size: 512, which is lower than the FP4 max-throughput setting (2048 at line 260). Verify this difference is intentional and reflects FP8's higher memory requirements. The comment at line 317 about reducingmax_num_tokensto 3072 should be validated for FP8 configs as well.
150-151: Confirm intentional differences between configuration sections.The Long context support section (ISL-64k and ISL-128k) retains explicit
batch_sizeslists, while the serving configurations now useenable_block_reuse: false. This is appropriate since these sections target different use cases (benchmarking vs. serving), but it's worth confirming this split design is intentional. The consistency with the learning from PR 7219 about respecting explicit batch sizes is good here.Also applies to: 177-177
Signed-off-by: jiahanc <173873397+jiahanc@users.noreply.github.com>
Signed-off-by: jiahanc <173873397+jiahanc@users.noreply.github.com>
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Signed-off-by: jiahanc <173873397+jiahanc@users.noreply.github.com> Signed-off-by: lkomali <lkomali@nvidia.com>
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Description
Update DS-R1 example guide to disable the KV reuse and reset cuda graph size
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