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@sunnyqgg sunnyqgg commented Oct 21, 2025

… py_seq_slot

Summary by CodeRabbit

  • Refactor

    • Optimized token indexing logic for improved alignment during speculative decoding.
  • Tests

    • Enabled previously skipped test to expand test coverage for disaggregated serving scenarios.

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… py_seq_slot

Signed-off-by: qgai <qgai@nvidia.com>
@sunnyqgg sunnyqgg requested a review from a team as a code owner October 21, 2025 03:54
@sunnyqgg sunnyqgg requested a review from zheyuf October 21, 2025 03:54
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/bot run --disable-fail-fast

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coderabbitai bot commented Oct 21, 2025

📝 Walkthrough

Walkthrough

Two changes: (1) Modified draft/target token indexing in model_drafter.py to use py_seq_slot instead of py_batch_idx, altering token alignment from batch-dimension to sequence-slot-dimension mapping; (2) Removed skip decorator from test_ngram in the test suite, enabling it to run.

Changes

Cohort / File(s) Change Summary
Speculative model token indexing
tensorrt_llm/_torch/speculative/model_drafter.py
Replaced draft_idx and target_idx indexing logic to use request.py_seq_slot instead of request.py_batch_idx when not in static draft loop, changing token placement from batch-based to sequence-slot-based alignment during speculative drafting.
Test suite enabling
tests/integration/defs/accuracy/test_disaggregated_serving.py
Removed skip decorator from test_ngram method, allowing test to execute as part of the test suite.

Estimated code review effort

🎯 2 (Simple) | ⏱️ ~12 minutes

Pre-merge checks and finishing touches

❌ Failed checks (1 warning)
Check name Status Explanation Resolution
Description Check ⚠️ Warning The PR description is substantially incomplete against the required template. The author has provided only a brief commit message ("… py_seq_slot") and left the critical sections empty: the Description section (which should explain the issue and solution) and the Test Coverage section (which should list relevant tests) are both blank. While the PR checklist is marked as complete with an [x], this appears premature given that the description lacks any actual explanation of what was changed and why, or documentation of test coverage. The author referenced "@coderabbitai summary" but did not include the generated summary or provide a human-written alternative explanation. The author should provide a substantive Description section explaining the dimension mismatch issue, the root cause, and how the py_seq_slot indexing change fixes it. Additionally, the Test Coverage section must clearly list which tests validate these changes (the test_ngram test that was unskipped and any tests that verify the model_drafter.py indexing fix). The PR checklist should only be marked complete after these required sections are properly filled out.
✅ Passed checks (2 passed)
Check name Status Explanation
Title Check ✅ Passed The PR title follows the required template format with a valid NVBugs ID, type indicator [fix], and a clear summary of the primary issue being addressed: a dimension mismatch in test_eagle3. While the title describes the bug being fixed rather than the specific implementation details (using py_seq_slot for token mapping), it is sufficiently clear and directly related to the main purpose of the changeset. A developer reviewing the history would understand that this PR addresses a dimension mismatch issue. The title is not misleading, though it could be more technically specific.
Docstring Coverage ✅ Passed Docstring coverage is 100.00% which is sufficient. The required threshold is 80.00%.
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  • tensorrt_llm/_torch/speculative/model_drafter.py (1 hunks)
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🔇 Additional comments (1)
tensorrt_llm/_torch/speculative/model_drafter.py (1)

502-504: Fix is correct and complete - dimension mismatch properly addressed.

Verification confirms the changes at lines 502-504 correctly resolve the dimension mismatch. The fix properly distinguishes between static and dynamic draft loops:

  • Dynamic mode (line 502): Uses request.py_seq_slot for tensor indexing, matching sequence slot assignment
  • Static mode (line 502): Uses req_idx from batch enumeration
  • Static-only method process_static_draft_outputs (lines 568-569): Correctly uses req_idx throughout since it only executes in static mode

The tensor indexing is now consistent across all code paths. No py_batch_idx remains in critical indexing operations, and the codebase properly separates static vs. dynamic indexing strategies.


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PR_Github #21994 [ run ] triggered by Bot. Commit: 218b8af

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PR_Github #21994 [ run ] completed with state SUCCESS. Commit: 218b8af
/LLM/main/L0_MergeRequest_PR pipeline #16584 completed with status: 'FAILURE'

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/bot run --disable-fail-fast

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PR_Github #22030 [ run ] triggered by Bot. Commit: 218b8af

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PR_Github #22030 [ run ] completed with state SUCCESS. Commit: 218b8af
/LLM/main/L0_MergeRequest_PR pipeline #16610 completed with status: 'SUCCESS'
Pipeline passed with automatic retried tests. Check the rerun report for details.

@longlee0622 longlee0622 merged commit 90080e0 into NVIDIA:main Oct 22, 2025
8 of 9 checks passed
yufeiwu-nv pushed a commit to yufeiwu-nv/TensorRT-LLM that referenced this pull request Oct 24, 2025
…a3_1_8BInstruct::test_eagle3 dimension mismatch (NVIDIA#8517)

Signed-off-by: qgai <qgai@nvidia.com>
Signed-off-by: yufeiwu-nv <230315618+yufeiwu-nv@users.noreply.github.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Nov 1, 2025
…a3_1_8BInstruct::test_eagle3 dimension mismatch (NVIDIA#8517)

Signed-off-by: qgai <qgai@nvidia.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Nov 3, 2025
…a3_1_8BInstruct::test_eagle3 dimension mismatch (NVIDIA#8517)

Signed-off-by: qgai <qgai@nvidia.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Nov 3, 2025
…a3_1_8BInstruct::test_eagle3 dimension mismatch (NVIDIA#8517)

Signed-off-by: qgai <qgai@nvidia.com>
dominicshanshan pushed a commit to dominicshanshan/TensorRT-LLM that referenced this pull request Nov 3, 2025
…a3_1_8BInstruct::test_eagle3 dimension mismatch (NVIDIA#8517)

Signed-off-by: qgai <qgai@nvidia.com>
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6 participants