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[arm64][cleanup] Remove CPURegister::Is and CPURegister::is
This removes {CPURegister::Is} and {CPURegister::is}, and just uses {CPURegister::operator==} instead. Drive-by: Use DCHECK_EQ and DCHECK_NE where possible. R=mstarzinger@chromium.org Bug: v8:9810 Change-Id: I03aad8b4223bd4ae37d468326a734f7a5c3c8061 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1916202 Reviewed-by: Jakob Gruber <jgruber@chromium.org> Reviewed-by: Michael Starzinger <mstarzinger@chromium.org> Commit-Queue: Clemens Backes <clemensb@chromium.org> Cr-Commit-Position: refs/heads/master@{#64956}
1 parent 1ccd139 commit 7762f53

11 files changed

Lines changed: 101 additions & 106 deletions

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‎src/builtins/arm64/builtins-arm64.cc‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1856,7 +1856,7 @@ void Builtins::Generate_FunctionPrototypeApply(MacroAssembler* masm) {
18561856
__ Bind(&no_arguments);
18571857
{
18581858
__ Mov(x0, 0);
1859-
DCHECK(receiver.Is(x1));
1859+
DCHECK_EQ(receiver, x1);
18601860
__ Jump(masm->isolate()->builtins()->Call(), RelocInfo::CODE_TARGET);
18611861
}
18621862
}
@@ -3362,7 +3362,7 @@ void CallApiFunctionAndReturn(MacroAssembler* masm, Register function_address,
33623362
const int kLevelOffset = AddressOffset(
33633363
ExternalReference::handle_scope_level_address(isolate), next_address);
33643364

3365-
DCHECK(function_address.is(x1) || function_address.is(x2));
3365+
DCHECK(function_address == x1 || function_address == x2);
33663366

33673367
Label profiler_enabled, end_profiler_check;
33683368
__ Mov(x10, ExternalReference::is_profiling_address(isolate));

‎src/codegen/arm64/assembler-arm64-inl.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -270,7 +270,7 @@ Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
270270
}
271271

272272
bool Operand::IsHeapObjectRequest() const {
273-
DCHECK_IMPLIES(heap_object_request_.has_value(), reg_.Is(NoReg));
273+
DCHECK_IMPLIES(heap_object_request_.has_value(), reg_ == NoReg);
274274
DCHECK_IMPLIES(heap_object_request_.has_value(),
275275
immediate_.rmode() == RelocInfo::FULL_EMBEDDED_OBJECT ||
276276
immediate_.rmode() == RelocInfo::CODE_TARGET);
@@ -283,7 +283,7 @@ HeapObjectRequest Operand::heap_object_request() const {
283283
}
284284

285285
bool Operand::IsImmediate() const {
286-
return reg_.Is(NoReg) && !IsHeapObjectRequest();
286+
return reg_ == NoReg && !IsHeapObjectRequest();
287287
}
288288

289289
bool Operand::IsShiftedRegister() const {
@@ -452,11 +452,11 @@ MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
452452
}
453453

454454
bool MemOperand::IsImmediateOffset() const {
455-
return (addrmode_ == Offset) && regoffset_.Is(NoReg);
455+
return (addrmode_ == Offset) && regoffset_ == NoReg;
456456
}
457457

458458
bool MemOperand::IsRegisterOffset() const {
459-
return (addrmode_ == Offset) && !regoffset_.Is(NoReg);
459+
return (addrmode_ == Offset) && regoffset_ != NoReg;
460460
}
461461

462462
bool MemOperand::IsPreIndex() const { return addrmode_ == PreIndex; }

‎src/codegen/arm64/assembler-arm64.cc‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,7 @@ MemOperand::PairResult MemOperand::AreConsistentForPair(
299299
DCHECK_LE(access_size_log2, 3);
300300
// Step one: check that they share the same base, that the mode is Offset
301301
// and that the offset is a multiple of access size.
302-
if (!operandA.base().Is(operandB.base()) || (operandA.addrmode() != Offset) ||
302+
if (operandA.base() != operandB.base() || (operandA.addrmode() != Offset) ||
303303
(operandB.addrmode() != Offset) ||
304304
((operandA.offset() & ((1 << access_size_log2) - 1)) != 0)) {
305305
return kNotPair;
@@ -752,7 +752,7 @@ void Assembler::blr(const Register& xn) {
752752
DCHECK(xn.Is64Bits());
753753
// The pattern 'blr xzr' is used as a guard to detect when execution falls
754754
// through the constant pool. It should not be emitted.
755-
DCHECK(!xn.Is(xzr));
755+
DCHECK_NE(xn, xzr);
756756
Emit(BLR | Rn(xn));
757757
}
758758

@@ -1209,7 +1209,7 @@ void Assembler::ldpsw(const Register& rt, const Register& rt2,
12091209
void Assembler::LoadStorePair(const CPURegister& rt, const CPURegister& rt2,
12101210
const MemOperand& addr, LoadStorePairOp op) {
12111211
// 'rt' and 'rt2' can only be aliased for stores.
1212-
DCHECK(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2));
1212+
DCHECK(((op & LoadStorePairLBit) == 0) || rt != rt2);
12131213
DCHECK(AreSameSizeAndType(rt, rt2));
12141214
DCHECK(IsImmLSPair(addr.offset(), CalcLSPairDataSize(op)));
12151215
int offset = static_cast<int>(addr.offset());
@@ -1222,8 +1222,8 @@ void Assembler::LoadStorePair(const CPURegister& rt, const CPURegister& rt2,
12221222
addrmodeop = LoadStorePairOffsetFixed;
12231223
} else {
12241224
// Pre-index and post-index modes.
1225-
DCHECK(!rt.Is(addr.base()));
1226-
DCHECK(!rt2.Is(addr.base()));
1225+
DCHECK_NE(rt, addr.base());
1226+
DCHECK_NE(rt2, addr.base());
12271227
DCHECK_NE(addr.offset(), 0);
12281228
if (addr.IsPreIndex()) {
12291229
addrmodeop = LoadStorePairPreIndexFixed;
@@ -1337,7 +1337,7 @@ void Assembler::stlr(const Register& rt, const Register& rn) {
13371337
void Assembler::stlxr(const Register& rs, const Register& rt,
13381338
const Register& rn) {
13391339
DCHECK(rn.Is64Bits());
1340-
DCHECK(!rs.Is(rt) && !rs.Is(rn));
1340+
DCHECK(rs != rt && rs != rn);
13411341
LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLXR_w : STLXR_x;
13421342
Emit(op | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
13431343
}
@@ -1365,7 +1365,7 @@ void Assembler::stlxrb(const Register& rs, const Register& rt,
13651365
DCHECK(rs.Is32Bits());
13661366
DCHECK(rt.Is32Bits());
13671367
DCHECK(rn.Is64Bits());
1368-
DCHECK(!rs.Is(rt) && !rs.Is(rn));
1368+
DCHECK(rs != rt && rs != rn);
13691369
Emit(STLXR_b | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
13701370
}
13711371

@@ -1392,7 +1392,7 @@ void Assembler::stlxrh(const Register& rs, const Register& rt,
13921392
DCHECK(rs.Is32Bits());
13931393
DCHECK(rt.Is32Bits());
13941394
DCHECK(rn.Is64Bits());
1395-
DCHECK(!rs.Is(rt) && !rs.Is(rn));
1395+
DCHECK(rs != rt && rs != rn);
13961396
Emit(STLXR_h | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
13971397
}
13981398

@@ -2282,7 +2282,7 @@ void Assembler::LoadStoreStructVerify(const VRegister& vt,
22822282
default:
22832283
UNREACHABLE();
22842284
}
2285-
DCHECK(!addr.regoffset().Is(NoReg) || addr.offset() == offset);
2285+
DCHECK(addr.regoffset() != NoReg || addr.offset() == offset);
22862286
}
22872287
#else
22882288
USE(vt);
@@ -3947,7 +3947,7 @@ void Assembler::LoadStore(const CPURegister& rt, const MemOperand& addr,
39473947
ExtendMode(ext) | ImmShiftLS((shift_amount > 0) ? 1 : 0));
39483948
} else {
39493949
// Pre-index and post-index modes.
3950-
DCHECK(!rt.Is(addr.base()));
3950+
DCHECK_NE(rt, addr.base());
39513951
if (IsImmLSUnscaled(addr.offset())) {
39523952
int offset = static_cast<int>(addr.offset());
39533953
if (addr.IsPreIndex()) {

‎src/codegen/arm64/macro-assembler-arm64-inl.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -390,7 +390,7 @@ void TurboAssembler::CmovX(const Register& rd, const Register& rn,
390390
DCHECK(!rd.IsSP());
391391
DCHECK(rd.Is64Bits() && rn.Is64Bits());
392392
DCHECK((cond != al) && (cond != nv));
393-
if (!rd.is(rn)) {
393+
if (rd != rn) {
394394
csel(rd, rn, rd, cond);
395395
}
396396
}
@@ -596,7 +596,7 @@ void TurboAssembler::Fmov(VRegister fd, VRegister fn) {
596596
// registers. fmov(s0, s0) is not a no-op because it clears the top word of
597597
// d0. Technically, fmov(d0, d0) is not a no-op either because it clears the
598598
// top of q0, but VRegister does not currently support Q registers.
599-
if (!fd.Is(fn) || !fd.Is64Bits()) {
599+
if (fd != fn || !fd.Is64Bits()) {
600600
fmov(fd, fn);
601601
}
602602
}

‎src/codegen/arm64/macro-assembler-arm64.cc‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,7 @@ void TurboAssembler::LogicalMacro(const Register& rd, const Register& rn,
165165

166166
// If the left-hand input is the stack pointer, we can't pre-shift the
167167
// immediate, as the encoding won't allow the subsequent post shift.
168-
PreShiftImmMode mode = rn.Is(sp) ? kNoShift : kAnyShift;
168+
PreShiftImmMode mode = rn == sp ? kNoShift : kAnyShift;
169169
Operand imm_operand = MoveImmediateForShiftedOp(temp, immediate, mode);
170170

171171
if (rd.IsSP()) {
@@ -327,7 +327,7 @@ void TurboAssembler::Mov(const Register& rd, const Operand& operand,
327327
// this case, the instruction is discarded.
328328
//
329329
// If sp is an operand, add #0 is emitted, otherwise, orr #0.
330-
if (!rd.Is(operand.reg()) ||
330+
if (rd != operand.reg() ||
331331
(rd.Is32Bits() && (discard_mode == kDontDiscardForSameWReg))) {
332332
Assembler::mov(rd, operand.reg());
333333
}
@@ -336,7 +336,7 @@ void TurboAssembler::Mov(const Register& rd, const Operand& operand,
336336
}
337337

338338
// Copy the result to the system stack pointer.
339-
if (!dst.Is(rd)) {
339+
if (dst != rd) {
340340
DCHECK(rd.IsSP());
341341
Assembler::mov(rd, dst);
342342
}
@@ -697,7 +697,7 @@ Operand TurboAssembler::MoveImmediateForShiftedOp(const Register& dst,
697697
void TurboAssembler::AddSubMacro(const Register& rd, const Register& rn,
698698
const Operand& operand, FlagsUpdate S,
699699
AddSubOp op) {
700-
if (operand.IsZero() && rd.Is(rn) && rd.Is64Bits() && rn.Is64Bits() &&
700+
if (operand.IsZero() && rd == rn && rd.Is64Bits() && rn.Is64Bits() &&
701701
!operand.NeedsRelocation(this) && (S == LeaveFlags)) {
702702
// The instruction would be a nop. Avoid generating useless code.
703703
return;
@@ -720,11 +720,11 @@ void TurboAssembler::AddSubMacro(const Register& rd, const Register& rn,
720720
// If the destination or source register is the stack pointer, we can
721721
// only pre-shift the immediate right by values supported in the add/sub
722722
// extend encoding.
723-
if (rd.Is(sp)) {
723+
if (rd == sp) {
724724
// If the destination is SP and flags will be set, we can't pre-shift
725725
// the immediate at all.
726726
mode = (S == SetFlags) ? kNoShift : kLimitShiftForSP;
727-
} else if (rn.Is(sp)) {
727+
} else if (rn == sp) {
728728
mode = kLimitShiftForSP;
729729
}
730730

@@ -910,7 +910,7 @@ void TurboAssembler::Adr(const Register& rd, Label* label, AdrHint hint) {
910910
}
911911

912912
void TurboAssembler::B(Label* label, BranchType type, Register reg, int bit) {
913-
DCHECK((reg.Is(NoReg) || type >= kBranchTypeFirstUsingReg) &&
913+
DCHECK((reg == NoReg || type >= kBranchTypeFirstUsingReg) &&
914914
(bit == -1 || type >= kBranchTypeFirstUsingBit));
915915
if (kBranchTypeFirstCondition <= type && type <= kBranchTypeLastCondition) {
916916
B(static_cast<Condition>(type), label);
@@ -1487,7 +1487,7 @@ void TurboAssembler::MovePair(Register dst0, Register src0, Register dst1,
14871487

14881488
void TurboAssembler::Swap(Register lhs, Register rhs) {
14891489
DCHECK(lhs.IsSameSizeAndType(rhs));
1490-
DCHECK(!lhs.Is(rhs));
1490+
DCHECK_NE(lhs, rhs);
14911491
UseScratchRegisterScope temps(this);
14921492
Register temp = temps.AcquireX();
14931493
Mov(temp, rhs);
@@ -1497,7 +1497,7 @@ void TurboAssembler::Swap(Register lhs, Register rhs) {
14971497

14981498
void TurboAssembler::Swap(VRegister lhs, VRegister rhs) {
14991499
DCHECK(lhs.IsSameSizeAndType(rhs));
1500-
DCHECK(!lhs.Is(rhs));
1500+
DCHECK_NE(lhs, rhs);
15011501
UseScratchRegisterScope temps(this);
15021502
VRegister temp = VRegister::no_reg();
15031503
if (lhs.IsS()) {
@@ -2179,8 +2179,8 @@ void MacroAssembler::InvokeFunctionCode(Register function, Register new_target,
21792179
InvokeFlag flag) {
21802180
// You can't call a function without a valid frame.
21812181
DCHECK(flag == JUMP_FUNCTION || has_frame());
2182-
DCHECK(function.is(x1));
2183-
DCHECK_IMPLIES(new_target.is_valid(), new_target.is(x3));
2182+
DCHECK_EQ(function, x1);
2183+
DCHECK_IMPLIES(new_target.is_valid(), new_target == x3);
21842184

21852185
// On function call, call into the debugger if necessary.
21862186
Label debug_hook, continue_after_hook;
@@ -2235,7 +2235,7 @@ void MacroAssembler::InvokeFunctionWithNewTarget(
22352235

22362236
// Contract with called JS functions requires that function is passed in x1.
22372237
// (See FullCodeGenerator::Generate().)
2238-
DCHECK(function.is(x1));
2238+
DCHECK_EQ(function, x1);
22392239

22402240
Register expected_parameter_count = x2;
22412241

@@ -2264,7 +2264,7 @@ void MacroAssembler::InvokeFunction(Register function,
22642264

22652265
// Contract with called JS functions requires that function is passed in x1.
22662266
// (See FullCodeGenerator::Generate().)
2267-
DCHECK(function.Is(x1));
2267+
DCHECK_EQ(function, x1);
22682268

22692269
// Set up the context.
22702270
LoadTaggedPointerField(cp,

‎src/codegen/arm64/register-arm64.h‎

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -150,19 +150,16 @@ class CPURegister : public RegisterBase<CPURegister, kRegAfterLast> {
150150
return reg_size_ == 128;
151151
}
152152
bool IsNone() const { return reg_type_ == kNoRegister; }
153-
constexpr bool Is(const CPURegister& other) const {
154-
return Aliases(other) && (reg_size_ == other.reg_size_);
155-
}
156153
constexpr bool Aliases(const CPURegister& other) const {
157154
return (reg_code_ == other.reg_code_) && (reg_type_ == other.reg_type_);
158155
}
159156

160157
constexpr bool operator==(const CPURegister& other) const {
161-
return Is(other);
158+
return RegisterBase::operator==(other) && reg_size_ == other.reg_size_ &&
159+
reg_type_ == other.reg_type_;
162160
}
163-
164161
constexpr bool operator!=(const CPURegister& other) const {
165-
return !(*this == other);
162+
return !operator==(other);
166163
}
167164

168165
bool IsZero() const;
@@ -203,8 +200,6 @@ class CPURegister : public RegisterBase<CPURegister, kRegAfterLast> {
203200

204201
bool IsSameSizeAndType(const CPURegister& other) const;
205202

206-
bool is(const CPURegister& other) const { return Is(other); }
207-
208203
protected:
209204
int reg_size_;
210205
RegisterType reg_type_;
@@ -455,8 +450,8 @@ class VRegister : public CPURegister {
455450
ASSERT_TRIVIALLY_COPYABLE(VRegister);
456451

457452
// No*Reg is used to indicate an unused argument, or an error case. Note that
458-
// these all compare equal (using the Is() method). The Register and VRegister
459-
// variants are provided for convenience.
453+
// these all compare equal. The Register and VRegister variants are provided for
454+
// convenience.
460455
constexpr Register NoReg = Register::no_reg();
461456
constexpr VRegister NoVReg = VRegister::no_reg();
462457
constexpr CPURegister NoCPUReg = CPURegister::no_reg();

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