Skip to content

Commit 1de07ae

Browse files
Milad FaCommit Bot
Milad Fa
authored and
Commit Bot
committed
PPC/s390: [wasm-simd] Implement i8x16.popcnt
Implementation for PPC will be added in a later CL. Port dd90d10 Original Commit Message: Code sequence from WebAssembly/simd#379, and exactly the same as x64, with minor tweaks for ExternalReferenceAsOperand. R=zhin@chromium.org, joransiu@ca.ibm.com, junyan@redhat.com, midawson@redhat.com BUG= LOG=N Change-Id: I2be8a9cf04d0b327c15f47c2575877925238353c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2672706 Reviewed-by: Junliang Yan <junyan@redhat.com> Commit-Queue: Milad Fa <mfarazma@redhat.com> Cr-Commit-Position: refs/heads/master@{#72510}
1 parent 357ba1b commit 1de07ae

6 files changed

Lines changed: 51 additions & 14 deletions

File tree

‎src/compiler/backend/ppc/instruction-selector-ppc.cc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2501,6 +2501,7 @@ void InstructionSelector::VisitI16x8ExtMulLowI8x16U(Node* node) {
25012501
void InstructionSelector::VisitI16x8ExtMulHighI8x16U(Node* node) {
25022502
UNIMPLEMENTED();
25032503
}
2504+
void InstructionSelector::VisitI8x16Popcnt(Node* node) { UNIMPLEMENTED(); }
25042505

25052506
void InstructionSelector::EmitPrepareResults(
25062507
ZoneVector<PushParameter>* results, const CallDescriptor* call_descriptor,

‎src/compiler/backend/s390/code-generator-s390.cc‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4282,6 +4282,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
42824282
break;
42834283
}
42844284
#undef SIGN_SELECT
4285+
case kS390_I8x16Popcnt: {
4286+
__ vpopct(i.OutputSimd128Register(), i.InputSimd128Register(0),
4287+
Condition(0), Condition(0), Condition(0));
4288+
break;
4289+
}
42854290
case kS390_StoreCompressTagged: {
42864291
CHECK(!instr->HasOutput());
42874292
size_t index = 0;

‎src/compiler/backend/s390/instruction-codes-s390.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -378,6 +378,7 @@ namespace compiler {
378378
V(S390_I8x16Shuffle) \
379379
V(S390_I8x16Swizzle) \
380380
V(S390_I8x16SignSelect) \
381+
V(S390_I8x16Popcnt) \
381382
V(S390_V64x2AllTrue) \
382383
V(S390_V32x4AllTrue) \
383384
V(S390_V16x8AllTrue) \

‎src/compiler/backend/s390/instruction-scheduler-s390.cc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -325,6 +325,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
325325
case kS390_I8x16Shuffle:
326326
case kS390_I8x16Swizzle:
327327
case kS390_I8x16SignSelect:
328+
case kS390_I8x16Popcnt:
328329
case kS390_V64x2AllTrue:
329330
case kS390_V32x4AllTrue:
330331
case kS390_V16x8AllTrue:

‎src/compiler/backend/s390/instruction-selector-s390.cc‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2533,6 +2533,7 @@ void InstructionSelector::VisitWord64AtomicStore(Node* node) {
25332533
V(I16x8UConvertI8x16High) \
25342534
V(I8x16Neg) \
25352535
V(I8x16Abs) \
2536+
V(I8x16Popcnt) \
25362537
V(S128Not)
25372538

25382539
#define SIMD_SHIFT_LIST(V) \

‎src/execution/s390/simulator-s390.cc‎

Lines changed: 42 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -778,20 +778,21 @@ void Simulator::EvalTableInit() {
778778
V(vuplh, VUPLH, 0xE7D5) /* type = VRR_A VECTOR UNPACK LOGICAL HIGH */ \
779779
V(vupl, VUPL, 0xE7D6) /* type = VRR_A VECTOR UNPACK LOW */ \
780780
V(vuph, VUPH, 0xE7D7) /* type = VRR_A VECTOR UNPACK HIGH */ \
781-
V(vmnl, VMNL, 0xE7FC) /* type = VRR_C VECTOR MINIMUM LOGICAL */ \
782-
V(vmxl, VMXL, 0xE7FD) /* type = VRR_C VECTOR MAXIMUM LOGICAL */ \
783-
V(vmn, VMN, 0xE7FE) /* type = VRR_C VECTOR MINIMUM */ \
784-
V(vmx, VMX, 0xE7FF) /* type = VRR_C VECTOR MAXIMUM */ \
785-
V(vceq, VCEQ, 0xE7F8) /* type = VRR_B VECTOR COMPARE EQUAL */ \
786-
V(vx, VX, 0xE76D) /* type = VRR_C VECTOR EXCLUSIVE OR */ \
787-
V(vchl, VCHL, 0xE7F9) /* type = VRR_B VECTOR COMPARE HIGH LOGICAL */ \
788-
V(vch, VCH, 0xE7FB) /* type = VRR_B VECTOR COMPARE HIGH */ \
789-
V(vo, VO, 0xE76A) /* type = VRR_C VECTOR OR */ \
790-
V(vn, VN, 0xE768) /* type = VRR_C VECTOR AND */ \
791-
V(vno, VNO, 0xE768B) /* type = VRR_C VECTOR NOR */ \
792-
V(vlc, VLC, 0xE7DE) /* type = VRR_A VECTOR LOAD COMPLEMENT */ \
793-
V(vsel, VSEL, 0xE78D) /* type = VRR_E VECTOR SELECT */ \
794-
V(vperm, VPERM, 0xE78C) /* type = VRR_E VECTOR PERMUTE */ \
781+
V(vpopct, VPOPCT, 0xE750) /* type = VRR_A VECTOR POPULATION COUNT */ \
782+
V(vmnl, VMNL, 0xE7FC) /* type = VRR_C VECTOR MINIMUM LOGICAL */ \
783+
V(vmxl, VMXL, 0xE7FD) /* type = VRR_C VECTOR MAXIMUM LOGICAL */ \
784+
V(vmn, VMN, 0xE7FE) /* type = VRR_C VECTOR MINIMUM */ \
785+
V(vmx, VMX, 0xE7FF) /* type = VRR_C VECTOR MAXIMUM */ \
786+
V(vceq, VCEQ, 0xE7F8) /* type = VRR_B VECTOR COMPARE EQUAL */ \
787+
V(vx, VX, 0xE76D) /* type = VRR_C VECTOR EXCLUSIVE OR */ \
788+
V(vchl, VCHL, 0xE7F9) /* type = VRR_B VECTOR COMPARE HIGH LOGICAL */ \
789+
V(vch, VCH, 0xE7FB) /* type = VRR_B VECTOR COMPARE HIGH */ \
790+
V(vo, VO, 0xE76A) /* type = VRR_C VECTOR OR */ \
791+
V(vn, VN, 0xE768) /* type = VRR_C VECTOR AND */ \
792+
V(vno, VNO, 0xE768B) /* type = VRR_C VECTOR NOR */ \
793+
V(vlc, VLC, 0xE7DE) /* type = VRR_A VECTOR LOAD COMPLEMENT */ \
794+
V(vsel, VSEL, 0xE78D) /* type = VRR_E VECTOR SELECT */ \
795+
V(vperm, VPERM, 0xE78C) /* type = VRR_E VECTOR PERMUTE */ \
795796
V(vbperm, VBPERM, 0xE785) /* type = VRR_C VECTOR BIT PERMUTE */ \
796797
V(vtm, VTM, 0xE7D8) /* type = VRR_A VECTOR TEST UNDER MASK */ \
797798
V(vesl, VESL, 0xE730) /* type = VRS_A VECTOR ELEMENT SHIFT LEFT */ \
@@ -3461,6 +3462,33 @@ EVALUATE(VUPLH) {
34613462
}
34623463
#undef CASE
34633464

3465+
template <class S>
3466+
void VectorPopulationCount(Simulator* sim, int dst, int src) {
3467+
FOR_EACH_LANE(i, S) {
3468+
sim->set_simd_register_by_lane<S>(
3469+
dst, i,
3470+
base::bits::CountPopulation(sim->get_simd_register_by_lane<S>(src, i)));
3471+
}
3472+
}
3473+
3474+
#define CASE(i, S) \
3475+
case i: \
3476+
VectorPopulationCount<S>(this, r1, r2); \
3477+
break;
3478+
EVALUATE(VPOPCT) {
3479+
DCHECK_OPCODE(VPOPCT);
3480+
DECODE_VRR_A_INSTRUCTION(r1, r2, m5, m4, m3);
3481+
USE(m5);
3482+
USE(m4);
3483+
switch (m3) {
3484+
CASE(0, uint8_t);
3485+
default:
3486+
UNREACHABLE();
3487+
}
3488+
return length;
3489+
}
3490+
#undef CASE
3491+
34643492
template <class S, class D>
34653493
void VectorUnpackLow(Simulator* sim, int dst, int src) {
34663494
constexpr size_t kItemCount = kSimd128Size / sizeof(D);

0 commit comments

Comments
 (0)