2025/09/01

1. Follow Demo board design and datasheet
        - Change L1, L2 to 600R/0.5A
2. 5V -> 3.3V LDO
	- Add U7, C23, C24
3. Getting power from host by 5.1k RD on CC.
	- Add R30 5.1k on CC1 of USB-C Receptacle
4. A method for being provider or receiver of 5V of Target device Provider path: 12k Rp for 5V@1.5A
	- Add SW1
	- Remove R5 on VCONN
	- Add R5 12k on SW
	- Change R4 to 5.1K."
5. Prioritizing Host 5V as default
	- Add D1, Q1, R31
6. Add power switch for 5V path output
	- Add U9, C31, C32
7. External Clock for FT4232
	- Add C27, C28, Y1
8. EC_VREF (3.3v) LDO
	- Add U8, C25, C26
9. Channel C and D don't have GPIO function.
	- "Move AP_UART_VREF_FORCE_3.3 to GPIO_L2 (but maybe we don't need it)"
10. LDO for SPI 3.3V and 1.8V
	- Add U11, C29, C30
11. Prevent activating SPI 3.3V and 1.8V at the same time.
	- Add U10(XOR), U12(AND), U13(AND)

2025/10/07

1. Add R33, R34, R35, R36 on USB+/- for banshee
2. Remove Q1, R31, D1
3. Add R29, Change U5 from 4 bit level shifter to OD buffer.
4. Remove netname AP_UART_VREF_FORCE_3.3 due to no need anymore.
5. Remove SW1, change R4 to 5.1K on CC and tie to GND, R32 to VCONN and tie to GND.
6. Change R27 to 1k from 100ohm
7. Remove U10(XOR), U12(AND), U13(AND)

2025/10/13

1. Remove R15, LED_AP_VREF and "AP_UART_VREF" net name
2. Adding Test points(TP2~TP18) to replace NC pins of U1 and U6
3. Adding footprint of parts
4. Correct Netname errors.
	SPI_VREF_FORCE_3.3_OUT -> SPI_VREF_FORCE_3.3
	SPI_VREF_FORCE_1.8_OUT -> SPI_VREF_FORCE_1.8
	SPI_OE_N -> FTDI_SPI_OE_N
5. DNC R35, R36
6. Add R15, R37, for isolating Banshee path and normal path
7. Add U10, C20, Netname "JTAG_SWD_SEL", Remove R22, R23, R24.
8. Change netname AP_UART_VREF to JTAG_SWD_SEL for LED indicator
9. Chnage JPD, JSPI PN to MOLEX_5051100692, JECDB to MOLEX_5051101097, which are similar to what Compal used.

2025/10/15

1. Remove U10, C20, Netname "JTAG_SWD_SEL"
2. Roll back design of SWDIO/JTAG(adding back R20, R21, TP1, R15, R22, R23)
3. Add JDB10 and JDB20
4.  Change JSPI and JPD to HRS_FH19C-6S-0.5SH
5. Change JECDB to Cvilux_CF35102D0RE-NH
6. Add TP19, TP20, TP21, TP22, TP23 on Unused pin of JTAG
7. Remove JTAG_SWD LED

10/16

1. Add JTAG Connection between JDB10 and JDB20

10/23

1. Remove JDB20, TP20~TP23
2. Change LED location reference to LED1~LED7, and Change LED2 to RGB because AP_SPI_VREF will have either 1.8v or 3.3v. Add R38, R39 for current limit.
3. Add footprint for X'tal 7M-12.000MAAJ and change C27, C28 to 18pF.
4. Change JECDB to HRS_FH19C-10S-0.5SH

10/31

1. Change LED2, LED7 to EAST1616RGBA1 because it's common cathode
2. Edit LED2, LED7 symbol to follow spec.
3. Change TP19 to EC_VREF net
4. Change SPI NET NAME
5. Change DUT_CCD SBU pins net name
6. Remove Test points for saving space
7. Renaming TP to align pin name

11/05

1. Rename JTAG netname
2. Change pin order of JPD1, JSPI1, JECDB1
3. Remove TPs

…orkComputer/FrameworkDebugger into pr-schematics_first_draft

12/16

1. Add a jumper for forcing power on to target device (J1)
2. add pull down on enable pins of FTDI. e.g. U11 (R15, R23)
3. add SPI Socket footprint  (TBD)
4. Add CC2 5.1k of Host connector (R24)
5. add pin header for EC Reset (J2)