|
| 1 | +/* |
| 2 | +------------------------------------ |
| 3 | +----- EXAMPLE 1: 4 BIT COUNTER ----- |
| 4 | +------------------------------------ |
| 5 | + |
| 6 | +---- MODEL DESIGN ------------------ |
| 7 | +module counter(clk, rst, en, out); |
| 8 | + |
| 9 | +input wire clk, rst, en; |
| 10 | +output [3:0] out; |
| 11 | + |
| 12 | +reg [3:0] reg_out; |
| 13 | + |
| 14 | +always@(posedge clk) |
| 15 | +begin |
| 16 | + if(rst == 1'b1) begin |
| 17 | + reg_out <= 4'b0000; |
| 18 | + end else if(en == 1'b1) begin |
| 19 | + reg_out <= reg_out + 1; |
| 20 | + end |
| 21 | +end |
| 22 | + |
| 23 | +endmodule |
| 24 | + |
| 25 | +---- MODEL TESTBENCH ------------- |
| 26 | +module counter_tb(); |
| 27 | + |
| 28 | +reg clk, rst, en; |
| 29 | +wire [3:0] out; |
| 30 | + |
| 31 | +counter my_counter(clk, rst, en, out); |
| 32 | + |
| 33 | +initial begin |
| 34 | + /* BIND Operation: Cold-start */ |
| 35 | + clk = 1; |
| 36 | + rst = 0; |
| 37 | + en = 0; |
| 38 | + #1; |
| 39 | + |
| 40 | + /* BIND operation: Reset */ |
| 41 | + rst = 1; |
| 42 | + #1; |
| 43 | + rst = 0; |
| 44 | + #1; |
| 45 | + |
| 46 | + /* BIND operation: Enable counting */ |
| 47 | + en = 1; |
| 48 | + #100; |
| 49 | + |
| 50 | + /* BIND operation: Finish counting */ |
| 51 | + en = 0; |
| 52 | + #1; |
| 53 | + $finish; |
| 54 | +end |
| 55 | + |
| 56 | +endmodule |
| 57 | + |
| 58 | +------------------------------------- |
| 59 | +**** Microcode sequence: |
| 60 | +opname | cycle | clk | rst | en | out | duration |
| 61 | +<NIL> X X X X XXXX | X |
| 62 | +COLD 0 1 0 0 XXXX | 1 |
| 63 | +RESET 1 1 1 0 0000 | 2 |
| 64 | +ENABLE 2 1 0 1 0000 | 100 |
| 65 | +FINISH 3 1 0 0 ???? | 1 |
| 66 | + |
| 67 | +**** Complete microcode sequence with sub-cycles: |
| 68 | +opname | cycle | clk | rst | en | out | duration |
| 69 | +<NIL> X X X X XXXX | X |
| 70 | + |
| 71 | +COLD 0.0 1 0 0 XXXX | 1 |
| 72 | + |
| 73 | +RESET.0 1.0 1 1 0 0000 | 1 |
| 74 | +RESET.1 1.1 1 0 0 0000 | 1 |
| 75 | + |
| 76 | +ENABLE 2.0 1 0 1 0000 | 100 |
| 77 | + |
| 78 | +FINISH 3.0 1 0 0 ???? | 1 |
| 79 | + |
| 80 | +(Side note: clk can be ignored, as it simply signifies a posedge trigger.) |
| 81 | +------------------------------------- |
| 82 | +**** TOTAL CLOCK CYCLES: 104 |
| 83 | +**** FINAL MICROCODE SEQUENCE (excluding clk): |
| 84 | +rst | en |
| 85 | + 0 0 |
| 86 | + 1 0 |
| 87 | + 0 0 |
| 88 | + 0 1 |
| 89 | + 0 0 |
| 90 | + |
| 91 | +**** EQUIVALENT (provided that each command format is 2 bits long): |
| 92 | +0010000100 |
| 93 | + |
| 94 | +**** OR |
| 95 | +00 |
| 96 | +10 |
| 97 | +00 |
| 98 | +01 |
| 99 | +00 |
| 100 | +------------------------------------- |
| 101 | +**** Intended testbench design: |
| 102 | + |
| 103 | +initial begin |
| 104 | + /* BIND Operation: Cold-start */ |
| 105 | + /* COLD operation is considered same as <NIL>, but inputs' states are known. We don't drive them. */ |
| 106 | + |
| 107 | + /* BIND operation: Reset */ |
| 108 | + /* The module's constructor deals with this */ |
| 109 | + |
| 110 | + /* BIND operation: Enable counting */ |
| 111 | + my_counter.enable(); // Output 01 |
| 112 | + #100; |
| 113 | + |
| 114 | + /* BIND operation: Finish counting */ |
| 115 | + /* FINISH operation is executed by the module's deconstructor by default. */ |
| 116 | + $finish; |
| 117 | +end |
| 118 | +------------------------------------- |
| 119 | +**** Intended binding mechanism: |
| 120 | + |
| 121 | +module counter(clk, rst, en, out); |
| 122 | + |
| 123 | +input wire clk, rst, en; |
| 124 | +output [3:0] out; |
| 125 | + |
| 126 | +reg [3:0] reg_out; |
| 127 | + |
| 128 | +/* Call trace: #1 */ |
| 129 | +fn counter() { /* NOTE : No inputs are involved, but it cold starts the module since it's the constructor. GENERATES MICROCODE: 00 */ |
| 130 | + /* Module constructor. Execute reset here */ |
| 131 | + /* NOTE: cold-start is already explicit by nature. |
| 132 | + Every newly instantiated module has its inputs all '0' or all '1' plus a 1 cycle delay. */ |
| 133 | + |
| 134 | + this = 0; /* Trigger '=' operator. 'this' is a reference to itself. This is equivalent to the reset operation. */ |
| 135 | +} |
| 136 | + |
| 137 | +/* Call trace: #4 */ |
| 138 | +fn ~counter() { /* NOTE : Inputs ARE involved, thus: GENERATES MICROCODE: 00 */ |
| 139 | + /* Terminate the counter. Note that it has no function arguments. */ |
| 140 | + en = 0; |
| 141 | +} |
| 142 | + |
| 143 | +/* Call trace: #2 */ |
| 144 | +fn = (u4 rval) { /* NOTE : GENERATES MICROCODE: 10,00 */ |
| 145 | + /* Binds '=' operator. Note that it has 1 function argument (obligatory). Operator is triggered by the testbench. */ |
| 146 | + /* Note: All non-driven wires will default to '0' or '1' in every new cycle. */ |
| 147 | + |
| 148 | + rst = 1; /* Raw input assignments are translated into microcode. rst's bit will be '1' on the 2nd entry of the microcode memory. */ |
| 149 | + #1; |
| 150 | + rst = 0; |
| 151 | + #1; |
| 152 | +} |
| 153 | + |
| 154 | +/* Call trace: #3 */ |
| 155 | +fn enable() { /* NOTE : Inputs ARE involved, thus: GENERATES MICROCODE: 01 */ |
| 156 | + /* Enable the counter. Note that it has no function arguments. */ |
| 157 | + en = 1; /* Raw input assignments are translated into microcode. en's bit will be '1' on the 4th entry of the microcode memory. */ |
| 158 | +} |
| 159 | + |
| 160 | +/* NOTE: All bindings are associated with the external module that drives this module's inputs. |
| 161 | + The module itself will not drive its own inputs. */ |
| 162 | + |
| 163 | +always@(posedge clk) |
| 164 | +begin |
| 165 | + if(rst == 1'b1) begin |
| 166 | + reg_out <= 4'b0000; |
| 167 | + end else if(en == 1'b1) begin |
| 168 | + reg_out <= reg_out + 1; |
| 169 | + end |
| 170 | +end |
| 171 | + |
| 172 | +endmodule |
| 173 | + |
| 174 | +*/ |
0 commit comments