Base implementation of benchmarks translated from C to RISCV RV32IM

IMplementation of Compiler and Scheduler based on already verified C programs.

Modified VLIWGenerator.cpp and VLIWGenerator.h. Added new build artifacts and output files, including binaries, object files, and analysis results for the CGRA compiler.

Removed custom and static C benchmark files in favor of new static memory versions for matrix sum and multiplication, avoiding function calls for RISC-V compatibility. Updated latency_config.yaml to use 'MUL' instead of 'MULTIPLY' and removed unused instructions. Documentation was revised to clarify supported instructions (RV32I + mul), update opcode mappings to standard RISC-V encodings, and reflect changes in operation descriptions. Added new static C benchmarks and corresponding assembly files.

Added RegisterInitializer module and integrated its source files into the build. Updated matrix_instance_static.s to use 99 instead of 3 for addi instructions. Updated makefile to include register_init sources. Output and build artifacts generated for new and updated tests.