diff options
| author | Anshuman Khandual <anshuman.khandual@arm.com> | 2025-06-06 10:56:02 +0530 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2025-06-10 18:14:43 +0100 |
| commit | b621b157b42f1fe398520cf499db88aa654c78e2 (patch) | |
| tree | fd0737494e69c188dd2b662b50856a772a105895 | |
| parent | 785302c1f7b9eceab3b72a8cb3d79eaf526fd2e3 (diff) | |
| download | boot-wrapper-aarch64-master.tar.gz | |
FEAT_SPE_FDS adds system register PMSDSFR_EL1. But accessing that system
register from EL2 and below exception levels, will trap into EL3 unless
MDCR_EL3.EnPMS3 is set.
Enable access to FEAT_SPE_FDS registers when they are implemented.
Cc: James Clark <james.clark@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: James Clark <james.clark@linaro.org>
Link: https://lore.kernel.org/r/20250606052602.3387225-1-anshuman.khandual@arm.com
[ Mark: remove unecessary comment and brackets ]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | arch/aarch64/include/asm/cpu.h | 4 | ||||
| -rw-r--r-- | arch/aarch64/init.c | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 2b3a659..ac50474 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -55,6 +55,7 @@ #define MDCR_EL3_NSTB_NS_NOTRAP (UL(3) << 24) #define MDCR_EL3_SBRBE_NOTRAP_NOPROHIBIT (UL(3) << 32) #define MDCR_EL3_ENPMSN BIT(36) +#define MDCR_EL3_ENPMS3 BIT(42) #define MDCR_EL3_EBWE BIT(43) #define MDCR_EL3_EnPM2 BIT(7) @@ -185,6 +186,9 @@ #define SCTLR_EL1_CP15BEN (1 << 5) +#define PMSIDR_EL1 s3_0_c9_c9_7 +#define PMSIDR_EL1_FDS BIT(7) + #ifdef KERNEL_32 /* * When booting a 32-bit kernel, EL1 uses AArch32 and registers which are diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index e1640a9..cb24f4e 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -146,6 +146,10 @@ static void cpu_init_el3(void) if (mrs_field(ID_AA64DFR0_EL1, PMSVER) >= 3) mdcr |= MDCR_EL3_ENPMSN; + if (mrs_field(ID_AA64DFR0_EL1, PMSVER) >= 1 && + mrs_field(PMSIDR_EL1, FDS)) + mdcr |= MDCR_EL3_ENPMS3; + if (mrs_field(ID_AA64DFR0_EL1, TRACEBUFFER)) mdcr |= MDCR_EL3_NSTB_NS_NOTRAP; |