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How to report a bug
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2
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19425
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May 27, 2024
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Reproducible GPU Validation: 95%+ Utilization on H100 with Ecosystem Compatibility
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0
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13
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December 19, 2025
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GPUDirect RDMA Bandwidth Bottleneck (~38Gbps) on ASUS WS X299 SAGE/10G with Tesla T4 + BlueField-2
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3
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20
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December 19, 2025
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Specifying L2 cache partition for SM
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2
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136
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December 19, 2025
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Looking for advice for CUDA performance tracking in CI/CD pipelines
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3
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40
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December 17, 2025
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Pinned memory throughput significantly lower on Ubuntu than on Windows
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23
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226
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December 17, 2025
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CUDA Green Context API | Memory Footprint
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2
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61
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December 17, 2025
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Double4 is deprecated, but the preferred double4_32a is unrecognized?
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6
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38
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December 16, 2025
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How to sync Cuda and Vulkan?
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2
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29
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December 16, 2025
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Nvcc, syntax error in cuda.h(7451): error: expected a ")"
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3
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53
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December 16, 2025
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Wmma vs Wgmma On H100 GPU
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4
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40
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December 15, 2025
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Thrust device allocator vs std allocator
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3
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41
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December 15, 2025
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Architectural insights needed: Why is the MIG 3g.71gb instance consistently the "Efficiency Sweet Spot" on H200?
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4
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74
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December 15, 2025
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Weekend project: Very accurate double-precision sincos() implementation for a restricted domain
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0
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27
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December 14, 2025
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Pixel Shader vs NPP - Which is faster for batch processing NV12 to RGB conversions and display directly to screen?
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5
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68
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December 14, 2025
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Register usage spike in SASS with divison slow/full path
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13
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205
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December 12, 2025
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Question about the cacheConfig value in nsight systems
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6
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55
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December 12, 2025
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Is the CUDA tile kernel submitted to GPU still using the cuLaunchKernel?
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2
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54
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December 12, 2025
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Unexpected results on cub::DeviceRadixSort::SortKeys and SortPairs with 128 bit keys
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5
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22
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December 12, 2025
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How many tensor cores to execute the wmma.mma.sync.aligned.{alayout}.{blayout}.m16n16k16 instruction？
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23
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163
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December 12, 2025
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__frsqrt_rn is not accurate 0.5ulp? I found a number
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4
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44
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December 10, 2025
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FFMA with Uniform register
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3
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75
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December 9, 2025
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Is it possible having compressible memory & memory pools over the same array on device?
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0
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29
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December 9, 2025
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cudaMemcpyBatchAsync cannot aggregate D2D copy operations
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13
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118
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December 9, 2025
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Training YOLO in the background
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1
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48
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December 8, 2025
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Deadlock when using cuStreamWaitValue32/cuStreamWriteValue32 for async cross-stream ordering
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8
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51
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December 8, 2025
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Implementing clang-tidy checks for CUDA C++ Guidelines for Safety Critical Programming
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3
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46
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December 8, 2025
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Question about CTA/warp lifecycle
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4
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49
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December 8, 2025
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Help needed to execute tcgen05.mma_cta_group::2 instructions
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0
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38
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December 7, 2025
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Which offers lower latency for NV12 to RGB conversion, NPP or CV-CUDA?
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1
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36
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December 5, 2025
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