A PCIe interface for the ECP5 FPGA written in nMigen
- Python 99.5%
- C++ 0.5%
| .vscode | ||
| Datasheets | ||
| Documentation | ||
| Firmware | ||
| Gateware | ||
| Images | ||
| ispCLOCK | ||
| PCIe-Adapter | ||
| Tests | ||
| .gitignore | ||
| .gitmodules | ||
| Block Diagram.svg | ||
| README.md | ||
| TODO | ||
ECP5-PCIe
ECP5 to PCIe interface development
The goal of this project is to provide a PCIe interface in Amaranth HDL.
Previous work
There already exists a PCIe physical layer by whitequark called Yumewatari and a TLP and DMA layer by enjoy-digital called litepcie written in omigen.
TODO
- Read through Yumewatari and litepcie code
- Read more of the PCIe spec and summarize relevant parts
- Get an ECP5 device capable of PCIe
- Currently an adapter for the ECP5 EVN to PCIe is being built
INSTALL
Execute python setup.py develop in the Gateware folder
SIMULATE
- Execute
python test_pcie_virtual.pyin the Tests folder to run the simulation - Execute
gtkwave test.gtkwto view the results
SETUP
See the Setup page in the Wiki
RUN
- Enable PCIe on the connected device (for example on the ROCKPro64 execute
pci initin u-boot) - Execute
python test_pcie_phy.py runin the Tests folder to upload the gateware to the ECP5 - Execute
python test_pcie_phy.py grabto get DLLPs received in the L0 state (and the time since it has been in the L0 state). Sometimes the last few results are invalid and the program doesn't halt, end it by pressingCtrl + C. It should show something like this:
Data is composed of the first symbol received in one clock cycle, its representation in hexadecimal, the same for the second symbol. The time is in clock cycles since entering L0, which are 8 ns each.
Time since L0 | RX data | TX data | Temperature
