It’s worth noting that the question raised by @barbie is very important(Is there still a significant difference between the aligned and unaligned reads once the data is in the cache ? The processor still has to do some work to get the data from the unaligned data in cache to its registers, so I imagine it could still have a measurable impact.).

I have made some try.
One experiment uses indent 0,1 and sequentially read uint32_t (4 bytes) data from 4MB buffer. The result shows there is no significant difference between the aligned (indent 0) and unaligned reads(indent 1. The indent is not multiple of 4, obviously there are many reads will cross a word (8 byte)).

In another experiment, I randomly generated some addresses with the remainder of 8 equal to 5 and some addresses equal to multiple of 8. Next, read uint32_t (4 bytes) data from the generated addresses. The results show there have significant difference between the aligned(read uint32_t from addresses which are equal to multiple of and unaligned reads (read uint32_t from addresses with the remainder of 8 equal to 5). There is a difference of about 17%.

I don’t know why experiment 1 and experiment 2 shows very different results. Just because sequential reading and randomly reading?

On the subject of typos, you have misspelled “quite” every time as “quiet”.